diff -urN linux-2.6.27/arch/arm/boot/compressed/head-xscale.S linux-2.6.27-vpac1/arch/arm/boot/compressed/head-xscale.S
--- linux-2.6.27/arch/arm/boot/compressed/head-xscale.S	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/boot/compressed/head-xscale.S	2008-11-26 16:05:40.000000000 +0100
@@ -6,6 +6,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/mach-types.h>
 
 		.section        ".start", "ax"
 
@@ -39,3 +40,8 @@
 		str	r1, [r0, #0x18]
 #endif
 
+#ifdef CONFIG_MACH_VPAC270
+                mov     r7, #(MACH_TYPE_VPAC270 & 0xFF00)
+                add     r7, r7, #(MACH_TYPE_VPAC270 & 0xFF)
+#endif
+
diff -urN linux-2.6.27/arch/arm/configs/vpac270_defconfig linux-2.6.27-vpac1/arch/arm/configs/vpac270_defconfig
--- linux-2.6.27/arch/arm/configs/vpac270_defconfig	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.27-vpac1/arch/arm/configs/vpac270_defconfig	2009-01-07 16:56:38.000000000 +0100
@@ -0,0 +1,1359 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.27-vpac1
+# Wed Jan  7 16:33:37 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ARCH_SUPPORTS_AOUT=y
+CONFIG_ZONE_DMA=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+# CONFIG_UID16 is not set
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+# CONFIG_SHMEM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
+# CONFIG_HAVE_IOREMAP_PROT is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
+# CONFIG_HAVE_DMA_ATTRS is not set
+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
+CONFIG_HAVE_CLK=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_TINY_SHMEM=y
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_MAINSTONE is not set
+CONFIG_MACH_VPAC270=y
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_TRIZEPS4 is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_ZYLONITE is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_PXA_EZX is not set
+CONFIG_PXA27x=y
+# CONFIG_PXA_PWM is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_OUTER_CACHE is not set
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA=y
+# CONFIG_PCMCIA_LOAD_CIS is not set
+CONFIG_PCMCIA_IOCTL=y
+
+#
+# PC-card bridges
+#
+CONFIG_PCMCIA_PXA2XX=y
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x20000
+CONFIG_ZBOOT_ROM_BSS=0xa0800000
+CONFIG_ZBOOT_ROM=y
+CONFIG_CMDLINE="mem=32M root=/dev/nfs ip=dhcp console=ttyS0,38400"
+# CONFIG_KEXEC is not set
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=y
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=y
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_SHARP_SL is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_BLK_DEV_IDECS=y
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDE_VPAC270=y
+CONFIG_BLK_DEV_IDEDMA=y
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=4
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=y
+# CONFIG_HOSTAP_FIRMWARE is not set
+CONFIG_HOSTAP_CS=y
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_AT24 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+CONFIG_FB_PXA_ANALOG=y
+# CONFIG_FB_PXA_TX14D14VM1BBA is not set
+# CONFIG_FB_PXA_FG0700A0DSSWAGT1 is not set
+# CONFIG_FB_PXA_VGA is not set
+CONFIG_FB_PXA_SVGA=y
+# CONFIG_FB_PXA_XGA is not set
+# CONFIG_FB_PXA_BPP8 is not set
+CONFIG_FB_PXA_BPP16=y
+# CONFIG_FB_PXA_SMARTPANEL is not set
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+# CONFIG_FB_W100 is not set
+# CONFIG_FB_AM200EPD is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+# CONFIG_SND_PCM_OSS_PLUGINS is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_PCM=y
+CONFIG_SND_PXA2XX_AC97=y
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+# CONFIG_MMC_SDHCI is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_VPAC270=y
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+# CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_SA1100 is not set
+# CONFIG_DMADEVICES is not set
+
+#
+# Voltage and Current regulators
+#
+# CONFIG_REGULATOR is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_LATENCYTOP is not set
+CONFIG_HAVE_FTRACE=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+# CONFIG_FTRACE is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_MANAGER=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff -urN linux-2.6.27/arch/arm/Kconfig.debug linux-2.6.27-vpac1/arch/arm/Kconfig.debug
--- linux-2.6.27/arch/arm/Kconfig.debug	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/Kconfig.debug	2008-11-27 14:52:11.000000000 +0100
@@ -71,6 +71,10 @@
 	  It does include a timeout to ensure that the system does not
 	  totally freeze when there is nothing connected to read.
 
+config EARLY_PRINTK
+	bool "Early PRINTK console support"
+	depends on DEBUG_LL
+
 config DEBUG_DC21285_PORT
 	bool "Kernel low-level debugging messages via footbridge serial port"
 	depends on DEBUG_LL && FOOTBRIDGE
diff -urN linux-2.6.27/arch/arm/kernel/early_printk.c linux-2.6.27-vpac1/arch/arm/kernel/early_printk.c
--- linux-2.6.27/arch/arm/kernel/early_printk.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.27-vpac1/arch/arm/kernel/early_printk.c	2008-11-27 14:57:29.000000000 +0100
@@ -0,0 +1,58 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Vpoipac Technologies a.s.
+ *
+ */
+#include <linux/console.h>
+#include <linux/init.h>
+
+#include <linux/serial_reg.h>
+#include <asm/processor.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+
+#define UART            FFUART
+#define CKEN_UART       CKEN6_FFUART
+#define GPIO_RX_MD      GPIO34_FFRXD_MD
+#define GPIO_TX_MD      GPIO39_FFTXD_MD
+
+
+static void pxa_serial_putchar(u8 c)
+{
+       static volatile unsigned long *port = (unsigned long *)&UART;
+
+        while (!(port[UART_LSR] & LSR_TDRQ))
+                cpu_relax();
+        port[UART_TX] = c;
+}
+
+
+static void early_console_write(struct console *con, const char *s, unsigned n)
+{
+       while (n-- && *s) {
+               if (*s == '\n')
+                       pxa_serial_putchar('\r');
+               pxa_serial_putchar(*s);
+               s++;
+       }
+}
+
+static struct console early_console = {
+       .name   = "early",
+       .write  = early_console_write,
+       .flags  = CON_PRINTBUFFER | CON_BOOT,
+       .index  = -1
+};
+
+void __init setup_early_printk(void)
+{
+       register_console(&early_console);
+}
+
+void __init disable_early_printk(void)
+{
+       unregister_console(&early_console);
+}
diff -urN linux-2.6.27/arch/arm/kernel/Makefile linux-2.6.27-vpac1/arch/arm/kernel/Makefile
--- linux-2.6.27/arch/arm/kernel/Makefile	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/kernel/Makefile	2008-11-27 14:53:37.000000000 +0100
@@ -44,5 +44,6 @@
 
 head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)	+= debug.o
+obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
 
 extra-y := $(head-y) init_task.o vmlinux.lds
diff -urN linux-2.6.27/arch/arm/kernel/setup.c linux-2.6.27-vpac1/arch/arm/kernel/setup.c
--- linux-2.6.27/arch/arm/kernel/setup.c	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/kernel/setup.c	2008-11-27 14:54:20.000000000 +0100
@@ -805,6 +805,12 @@
 	struct machine_desc *mdesc;
 	char *from = default_command_line;
 
+#ifdef CONFIG_EARLY_PRINTK
+	{
+		extern void setup_early_printk(void);
+		setup_early_printk();
+	}
+#endif
 	setup_processor();
 	mdesc = setup_machine(machine_arch_type);
 	machine_name = mdesc->name;
diff -urN linux-2.6.27/arch/arm/mach-pxa/cpu-pxa.c linux-2.6.27-vpac1/arch/arm/mach-pxa/cpu-pxa.c
--- linux-2.6.27/arch/arm/mach-pxa/cpu-pxa.c	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/mach-pxa/cpu-pxa.c	2008-11-26 13:26:43.000000000 +0100
@@ -12,7 +12,7 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
+ * 
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
@@ -21,12 +21,13 @@
  *   31-Jul-2002 : Initial version [FB]
  *   29-Jan-2003 : added PXA255 support [FB]
  *   20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
- *
+ *   11-Jan-2006 : v2.6, support for PXA27x processor up to 624MHz (Bill Reese, Hewlett Packard)
+ * 
  * Note:
  *   This driver may change the memory bus clock rate, but will not do any
  *   platform specific access timing changes... for example if you have flash
  *   memory connected to CS0, you will need to register a platform specific
- *   notifier which will adjust the memory access strobes to maintain a
+ *   notifier which will adjust the memory access strobes to maintain a 
  *   minimum strobe width.
  *
  */
@@ -38,373 +39,380 @@
 #include <linux/cpufreq.h>
 
 #include <mach/hardware.h>
+
 #include <mach/pxa-regs.h>
 #include <mach/pxa2xx-regs.h>
 
-#ifdef DEBUG
-static unsigned int freq_debug;
-module_param(freq_debug, uint, 0);
-MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
-#else
-#define freq_debug  0
-#endif
-
-static unsigned int pxa27x_maxfreq;
-module_param(pxa27x_maxfreq, uint, 0);
-MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
-		 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
-
-typedef struct {
-	unsigned int khz;
-	unsigned int membus;
-	unsigned int cccr;
-	unsigned int div2;
-	unsigned int cclkcfg;
-} pxa_freqs_t;
-
-/* Define the refresh period in mSec for the SDRAM and the number of rows */
-#define SDRAM_TREF	64	/* standard 64ms SDRAM */
-#define SDRAM_ROWS	4096	/* 64MB=8192 32MB=4096 */
-
-#define CCLKCFG_TURBO		0x1
-#define CCLKCFG_FCS		0x2
-#define CCLKCFG_HALFTURBO	0x4
-#define CCLKCFG_FASTBUS		0x8
-#define MDREFR_DB2_MASK		(MDREFR_K2DB2 | MDREFR_K1DB2)
-#define MDREFR_DRI_MASK		0xFFF
-
 /*
- * PXA255 definitions
+ * This comes from generic.h in this directory.
  */
-/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
-#define CCLKCFG			CCLKCFG_TURBO | CCLKCFG_FCS
+extern unsigned int get_clk_frequency_khz(int info);
 
-static pxa_freqs_t pxa255_run_freqs[] =
-{
-	/* CPU   MEMBUS  CCCR  DIV2 CCLKCFG	   run  turbo PXbus SDRAM */
-	{ 99500,  99500, 0x121, 1,  CCLKCFG},	/*  99,   99,   50,   50  */
-	{132700, 132700, 0x123, 1,  CCLKCFG},	/* 133,  133,   66,   66  */
-	{199100,  99500, 0x141, 0,  CCLKCFG},	/* 199,  199,   99,   99  */
-	{265400, 132700, 0x143, 1,  CCLKCFG},	/* 265,  265,  133,   66  */
-	{331800, 165900, 0x145, 1,  CCLKCFG},	/* 331,  331,  166,   83  */
-	{398100,  99500, 0x161, 0,  CCLKCFG},	/* 398,  398,  196,   99  */
-};
+//#define DEBUG  7
+
+#ifdef DEBUG
+  static unsigned int freq_debug = DEBUG;
+  module_param(freq_debug, int, 0644);
+  MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
+#else
+  #define freq_debug  0
+#endif  
 
-/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
-static pxa_freqs_t pxa255_turbo_freqs[] =
+typedef struct
 {
-	/* CPU   MEMBUS  CCCR  DIV2 CCLKCFG	   run  turbo PXbus SDRAM */
-	{ 99500, 99500,  0x121, 1,  CCLKCFG},	/*  99,   99,   50,   50  */
-	{199100, 99500,  0x221, 0,  CCLKCFG},	/*  99,  199,   50,   99  */
-	{298500, 99500,  0x321, 0,  CCLKCFG},	/*  99,  287,   50,   99  */
-	{298600, 99500,  0x1c1, 0,  CCLKCFG},	/* 199,  287,   99,   99  */
-	{398100, 99500,  0x241, 0,  CCLKCFG},	/* 199,  398,   99,   99  */
-};
+  unsigned int khz;     /* CPU frequency                                   */
+  unsigned int membus;  /* memory bus frequency                            */
+  unsigned int cccr;    /* new CCLKCFG setting                             */
+  unsigned int div2;    /* alter memory controller settings to divide by 2 */
+  unsigned int cclkcfg; /* new CCLKCFG setting                             */
+} pxa_freqs_t;
 
-#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
-#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
+/* Define the refresh period in mSec for the SDRAM and the number of rows */
+#define SDRAM_TREF          64      /* standard 64ms SDRAM */
+#if defined(CONFIG_MACH_H4700) || defined(CONFIG_ARCH_H2200)
+#define SDRAM_ROWS          8192    /* hx4700 uses 2 64Mb DRAMs, 8912 rows */
+#else
+#define SDRAM_ROWS          4096    /* 64MB=8192 32MB=4096 */ 
+#endif
+#define MDREFR_DRI(x)       (((x*SDRAM_TREF/SDRAM_ROWS - 31)/32))
 
-static struct cpufreq_frequency_table
-	pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
-static struct cpufreq_frequency_table
-	pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
+#define CCLKCFG_TURBO       0x1
+#define CCLKCFG_FCS         0x2
+#define CCLKCFG_HALFTURBO   0x4
+#define CCLKCFG_FASTBUS     0x8
+#define MDREFR_DB2_MASK     (MDREFR_K2DB2 | MDREFR_K1DB2)
+#define MDREFR_DRI_MASK     0xFFF
+#define PXA25x_CCLKCFG      CCLKCFG_TURBO | CCLKCFG_FCS
 
 /*
- * PXA270 definitions
- *
  * For the PXA27x:
  * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
  *
  * A = 0 => memory controller clock from table 3-7,
  * A = 1 => memory controller clock = system bus clock
- * Run mode frequency	= 13 MHz * L
+ * Run mode frequency   = 13 MHz * L
  * Turbo mode frequency = 13 MHz * L * N
  * System bus frequency = 13 MHz * L / (B + 1)
+ * System initialized by bootldr to:
  *
- * In CCCR:
+ * In CCCR: 
  * A = 1
- * L = 16	  oscillator to run mode ratio
- * 2N = 6	  2 * (turbo mode to run mode ratio)
+ * L = 16         oscillator to run mode ratio
+ * 2N = 6         2 * (turbo mode to run mode ratio)
  *
  * In CCLKCFG:
- * B = 1	  Fast bus mode
- * HT = 0	  Half-Turbo mode
- * T = 1	  Turbo mode
- *
+ * B = 1          Fast bus mode
+ * HT = 0         Half-Turbo mode
+ * T = 1          Turbo mode
+ * 
  * For now, just support some of the combinations in table 3-7 of
  * PXA27x Processor Family Developer's Manual to simplify frequency
  * change sequences.
+ * 
+ * Specify 2N in the PXA27x_CCCR macro, not N!
  */
 #define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
-#define CCLKCFG2(B, HT, T) \
-  (CCLKCFG_FCS | \
-   ((B)  ? CCLKCFG_FASTBUS : 0) | \
-   ((HT) ? CCLKCFG_HALFTURBO : 0) | \
-   ((T)  ? CCLKCFG_TURBO : 0))
-
-static pxa_freqs_t pxa27x_freqs[] = {
-	{104000, 104000, PXA27x_CCCR(1,	 8, 2), 0, CCLKCFG2(1, 0, 1)},
-	{156000, 104000, PXA27x_CCCR(1,	 8, 6), 0, CCLKCFG2(1, 1, 1)},
-	{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)},
-	{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)},
-	{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)},
-	{520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)},
-	{624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)}
-};
-
-#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
-static struct cpufreq_frequency_table
-	pxa27x_freq_table[NUM_PXA27x_FREQS+1];
-
-extern unsigned get_clk_frequency_khz(int info);
-
-static void find_freq_tables(struct cpufreq_policy *policy,
-			     struct cpufreq_frequency_table **freq_table,
-			     pxa_freqs_t **pxa_freqs)
-{
-	if (cpu_is_pxa25x()) {
-		if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
-			*pxa_freqs = pxa255_run_freqs;
-			*freq_table = pxa255_run_freq_table;
-		} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
-			*pxa_freqs = pxa255_turbo_freqs;
-			*freq_table = pxa255_turbo_freq_table;
-		} else {
-			printk("CPU PXA: Unknown policy found. "
-			       "Using CPUFREQ_POLICY_PERFORMANCE\n");
-			*pxa_freqs = pxa255_run_freqs;
-			*freq_table = pxa255_run_freq_table;
-		}
-	}
-	if (cpu_is_pxa27x()) {
-		*pxa_freqs = pxa27x_freqs;
-		*freq_table = pxa27x_freq_table;
-	}
-}
-
-static void pxa27x_guess_max_freq(void)
-{
-	if (!pxa27x_maxfreq) {
-		pxa27x_maxfreq = 416000;
-		printk(KERN_INFO "PXA CPU 27x max frequency not defined "
-		       "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
-		       pxa27x_maxfreq);
-	} else {
-		pxa27x_maxfreq *= 1000;
-	}
-}
+#define PXA27x_CCLKCFG(B, HT, T) (B << 3 |  HT << 2 | CCLKCFG_FCS | T)
 
-static u32 mdrefr_dri(unsigned int freq)
+/*
+ * Valid frequency assignments
+ */
+static pxa_freqs_t pxa2xx_freqs[] =
 {
-	u32 dri = 0;
+    /* CPU   MEMBUS  CCCR  DIV2*/
+#if defined(CONFIG_PXA25x)
+#if defined(CONFIG_PXA25x_ALTERNATE_FREQS)
+    { 99500, 99500,  0x121, 1, PXA25x_CCLKCFG}, /* run=99,  turbo= 99, PXbus=50, SDRAM=50 */
+    {199100, 99500,  0x221, 0, PXA25x_CCLKCFG}, /* run=99,  turbo=199, PXbus=50, SDRAM=99 */
+    {298500, 99500,  0x321, 0, PXA25x_CCLKCFG}, /* run=99,  turbo=287, PXbus=50, SDRAM=99 */
+    {298600, 99500,  0x1c1, 0, PXA25x_CCLKCFG}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */
+    {398100, 99500,  0x241, 0, PXA25x_CCLKCFG}  /* run=199, turbo=398, PXbus=99, SDRAM=99 */
+#else
+    { 99500,  99500, 0x121, 1, PXA25x_CCLKCFG}, /* run= 99, turbo= 99, PXbus=50,  SDRAM=50 */
+    {132700, 132700, 0x123, 1, PXA25x_CCLKCFG}, /* run=133, turbo=133, PXbus=66,  SDRAM=66 */
+    {199100,  99500, 0x141, 0, PXA25x_CCLKCFG}, /* run=199, turbo=199, PXbus=99,  SDRAM=99 */
+    {265400, 132700, 0x143, 1, PXA25x_CCLKCFG}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */
+    {331800, 165900, 0x145, 1, PXA25x_CCLKCFG}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */
+    {398100,  99500, 0x161, 0, PXA25x_CCLKCFG}  /* run=398, turbo=398, PXbus=196, SDRAM=99 */
+#endif
+#elif defined(CONFIG_PXA27x)
+    {104000, 104000, PXA27x_CCCR(1,  8, 2), 0, PXA27x_CCLKCFG(1, 0, 1)},
+    {156000, 104000, PXA27x_CCCR(1,  8, 6), 0, PXA27x_CCLKCFG(1, 1, 1)},
+    {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, PXA27x_CCLKCFG(0, 0, 1)},
+    {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, PXA27x_CCLKCFG(1, 0, 1)},
+    {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, PXA27x_CCLKCFG(1, 0, 1)},
+    {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, PXA27x_CCLKCFG(1, 0, 1)},
+    {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, PXA27x_CCLKCFG(1, 0, 1)}
+#endif
+};
+#define NUM_FREQS (sizeof(pxa2xx_freqs)/sizeof(pxa_freqs_t))
 
-	if (cpu_is_pxa25x())
-		dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32));
-	if (cpu_is_pxa27x())
-		dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32;
-	return dri;
-}
+static struct cpufreq_frequency_table pxa2xx_freq_table[NUM_FREQS+1];
 
 /* find a valid frequency point */
 static int pxa_verify_policy(struct cpufreq_policy *policy)
 {
-	struct cpufreq_frequency_table *pxa_freqs_table;
-	pxa_freqs_t *pxa_freqs;
-	int ret;
-
-	find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs);
-	ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
-
-	if (freq_debug)
-		pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
-			 policy->min, policy->max);
+    int ret;
+
+    ret=cpufreq_frequency_table_verify(policy, pxa2xx_freq_table);
+    
+    if(freq_debug) {
+        printk("Verified CPU policy: %dKhz min to %dKhz max\n",
+            policy->min, policy->max);
+    }
 
-	return ret;
+    return ret;
 }
 
-static unsigned int pxa_cpufreq_get(unsigned int cpu)
+static int pxa_set_target(struct cpufreq_policy *policy,
+                 unsigned int target_freq,
+                 unsigned int relation)
 {
-	return get_clk_frequency_khz(0);
+    int idx;
+    cpumask_t cpus_allowed, allowedcpuset;
+    int cpu = policy->cpu;
+    struct cpufreq_freqs freqs;
+    unsigned long flags;
+    unsigned int unused;
+    unsigned int preset_mdrefr, postset_mdrefr, cclkcfg;
+
+    if(freq_debug) {
+      printk ("CPU PXA: target freq %d\n", target_freq);
+      printk ("CPU PXA: relation %d\n", relation);
+    }
+
+    /*
+     * Save this threads cpus_allowed mask.
+     */
+    cpus_allowed = current->cpus_allowed;
+
+    /*
+     * Bind to the specified CPU.  When this call returns,
+     * we should be running on the right CPU.
+     */
+    cpus_clear (allowedcpuset);
+    cpu_set (cpu, allowedcpuset);
+    set_cpus_allowed(current, allowedcpuset);
+    BUG_ON(cpu != smp_processor_id());
+
+    /* Lookup the next frequency */
+    if (cpufreq_frequency_table_target(policy, pxa2xx_freq_table, 
+                                       target_freq, relation, &idx)) {
+      return -EINVAL;
+    }
+
+    freqs.old = policy->cur;
+    freqs.new = pxa2xx_freqs[idx].khz;
+    freqs.cpu = policy->cpu;  
+    if(freq_debug) {
+        printk(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", 
+            freqs.new/1000, (pxa2xx_freqs[idx].div2) ? 
+            (pxa2xx_freqs[idx].membus/2000) : 
+            (pxa2xx_freqs[idx].membus/1000));
+    }
+
+    /* 
+     * Tell everyone what we're about to do... 
+     * you should add a notify client with any platform specific 
+     * Vcc changing capability
+     */
+    cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+    /* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
+     * we need to preset the smaller DRI before the change.  If we're speeding
+     * up we need to set the larger DRI value after the change.  
+     */
+    preset_mdrefr = postset_mdrefr = MDREFR;
+    if((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa2xx_freqs[idx].membus)) {    
+        preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | 
+                        MDREFR_DRI(pxa2xx_freqs[idx].membus);
+    }
+    postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | 
+                    MDREFR_DRI(pxa2xx_freqs[idx].membus);
+    
+    /* If we're dividing the memory clock by two for the SDRAM clock, this
+     * must be set prior to the change.  Clearing the divide must be done
+     * after the change.
+     */
+    if(pxa2xx_freqs[idx].div2) {
+      /*
+       * Potentially speeding up memory clock, so slow down the memory
+       * before speeding up the clock.
+       */
+      preset_mdrefr  |= MDREFR_DB2_MASK | MDREFR_K0DB4;
+      preset_mdrefr  &= ~MDREFR_K0DB2;
+
+      postset_mdrefr |= MDREFR_DB2_MASK | MDREFR_K0DB4;
+      postset_mdrefr &= ~MDREFR_K0DB2;
+    } else { 
+      /*
+       * Potentially slowing down memory clock.  Wait until after the change
+       * to speed up the memory.
+       */
+      postset_mdrefr &= ~MDREFR_DB2_MASK; 
+      postset_mdrefr &= ~MDREFR_K0DB4;
+      postset_mdrefr |= MDREFR_K0DB2;
+    }
+
+    cclkcfg = pxa2xx_freqs[idx].cclkcfg;
+
+    if (freq_debug) {
+      printk (KERN_INFO "CPU PXA writing 0x%08x to CCCR\n",
+              pxa2xx_freqs[idx].cccr);
+      printk (KERN_INFO "CPU PXA writing 0x%08x to CCLKCFG\n",
+              pxa2xx_freqs[idx].cclkcfg);
+      printk (KERN_INFO "CPU PXA writing 0x%08x to MDREFR before change\n",
+              preset_mdrefr);
+      printk (KERN_INFO "CPU PXA writing 0x%08x to MDREFR after change\n",
+              postset_mdrefr);
+    }
+    
+    local_irq_save(flags);
+    
+    /* Set new the CCCR */
+    CCCR = pxa2xx_freqs[idx].cccr;
+
+    /*
+     * Should really set both of PMCR[xIDAE] while changing the core frequency
+     */
+
+    /*
+     * TODO: On the PXA27x: If we're setting half-turbo mode and changing the
+     * core frequency at the same time we must split it up into two operations.
+     * The current values in the pxa2xx_freqs table don't do this, so the code
+     * is unimplemented.
+     */
+
+    __asm__ __volatile__("                                  \
+        ldr r4, [%1] ;  /* load MDREFR */                   \
+        b   2f ;                                            \
+        .align  5 ;                                         \
+1:                                                          \
+        str %3, [%1] ;          /* preset the MDREFR */     \
+        mcr p14, 0, %2, c6, c0, 0 ; /* set CCLKCFG[FCS] */  \
+        str %4, [%1] ;          /* postset the MDREFR */    \
+                                                            \
+        b   3f       ;                                      \
+2:      b   1b       ;                                      \
+3:      nop          ;                                      \
+        "                                                                            
+        : "=&r" (unused)                                                             
+        : "r" (&MDREFR), "r" (cclkcfg), \
+          "r" (preset_mdrefr), "r" (postset_mdrefr)             
+        : "r4", "r5");
+    local_irq_restore(flags);
+
+    if (freq_debug) {
+      printk (KERN_INFO "CPU PXA Frequency change successful\n");
+      printk (KERN_INFO "CPU PXA new CCSR 0x%08x\n", CCSR);
+    }
+
+    /*
+     * Restore the CPUs allowed mask.
+     */
+    set_cpus_allowed(current, cpus_allowed);
+
+    /* 
+     * Tell everyone what we've just done... 
+     * you should add a notify client with any platform specific 
+     * SDRAM refresh timer adjustments
+     */
+    cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+    return 0;
 }
 
-static int pxa_set_target(struct cpufreq_policy *policy,
-			  unsigned int target_freq,
-			  unsigned int relation)
+static int pxa_cpufreq_init(struct cpufreq_policy *policy)
 {
-	struct cpufreq_frequency_table *pxa_freqs_table;
-	pxa_freqs_t *pxa_freq_settings;
-	struct cpufreq_freqs freqs;
-	unsigned int idx;
-	unsigned long flags;
-	unsigned int new_freq_cpu, new_freq_mem;
-	unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
-
-	/* Get the current policy */
-	find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings);
-
-	/* Lookup the next frequency */
-	if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
-					   target_freq, relation, &idx)) {
-		return -EINVAL;
-	}
-
-	new_freq_cpu = pxa_freq_settings[idx].khz;
-	new_freq_mem = pxa_freq_settings[idx].membus;
-	freqs.old = policy->cur;
-	freqs.new = new_freq_cpu;
-	freqs.cpu = policy->cpu;
-
-	if (freq_debug)
-		pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
-			 "(SDRAM %d Mhz)\n",
-			 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
-			 (new_freq_mem / 2000) : (new_freq_mem / 1000));
-
-	/*
-	 * Tell everyone what we're about to do...
-	 * you should add a notify client with any platform specific
-	 * Vcc changing capability
-	 */
-	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-	/* Calculate the next MDREFR.  If we're slowing down the SDRAM clock
-	 * we need to preset the smaller DRI before the change.	 If we're
-	 * speeding up we need to set the larger DRI value after the change.
-	 */
-	preset_mdrefr = postset_mdrefr = MDREFR;
-	if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
-		preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
-		preset_mdrefr |= mdrefr_dri(new_freq_mem);
-	}
-	postset_mdrefr =
-		(postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
-
-	/* If we're dividing the memory clock by two for the SDRAM clock, this
-	 * must be set prior to the change.  Clearing the divide must be done
-	 * after the change.
-	 */
-	if (pxa_freq_settings[idx].div2) {
-		preset_mdrefr  |= MDREFR_DB2_MASK;
-		postset_mdrefr |= MDREFR_DB2_MASK;
-	} else {
-		postset_mdrefr &= ~MDREFR_DB2_MASK;
-	}
-
-	local_irq_save(flags);
-
-	/* Set new the CCCR and prepare CCLKCFG */
-	CCCR = pxa_freq_settings[idx].cccr;
-	cclkcfg = pxa_freq_settings[idx].cclkcfg;
-
-	asm volatile("							\n\
-		ldr	r4, [%1]		/* load MDREFR */	\n\
-		b	2f						\n\
-		.align	5						\n\
-1:									\n\
-		str	%3, [%1]		/* preset the MDREFR */	\n\
-		mcr	p14, 0, %2, c6, c0, 0	/* set CCLKCFG[FCS] */	\n\
-		str	%4, [%1]		/* postset the MDREFR */ \n\
-									\n\
-		b	3f						\n\
-2:		b	1b						\n\
-3:		nop							\n\
-	  "
-		     : "=&r" (unused)
-		     : "r" (&MDREFR), "r" (cclkcfg),
-		       "r" (preset_mdrefr), "r" (postset_mdrefr)
-		     : "r4", "r5");
-	local_irq_restore(flags);
-
-	/*
-	 * Tell everyone what we've just done...
-	 * you should add a notify client with any platform specific
-	 * SDRAM refresh timer adjustments
-	 */
-	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+    cpumask_t cpus_allowed, allowedcpuset;
+    unsigned int cpu = policy->cpu;
+    int i;
+    unsigned int cclkcfg;
+
+    cpus_allowed = current->cpus_allowed;
+
+    cpus_clear (allowedcpuset);
+    cpu_set (cpu, allowedcpuset);
+    set_cpus_allowed(current, allowedcpuset);
+    BUG_ON(cpu != smp_processor_id());
+
+    /* set default governor and cpuinfo */
+    policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+    policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
+    policy->cur = get_clk_frequency_khz(0); /* current freq */
+
+    /* Generate the cpufreq_frequency_table struct */
+    for(i=0;i<NUM_FREQS;i++) {
+        pxa2xx_freq_table[i].frequency = pxa2xx_freqs[i].khz;
+        pxa2xx_freq_table[i].index = i;    
+    }
+    pxa2xx_freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+    /*
+     * Set the policy's minimum and maximum frequencies from the tables
+     * just constructed.  This sets cpuinfo.mxx_freq, min and max.
+     */
+    cpufreq_frequency_table_cpuinfo (policy, pxa2xx_freq_table);
+    
+    set_cpus_allowed(current, cpus_allowed);
+    printk(KERN_INFO "PXA CPU frequency change support initialized\n");
+
+    if (freq_debug) {
+      printk (KERN_INFO "PXA CPU initial CCCR 0x%08x\n", CCCR);
+      asm 
+	(
+	 "mrc p14, 0, %0, c6, c0, 0 ; /* read CCLKCFG from CP14 */ "
+	 : "=r" (cclkcfg) : 
+	 );
+      printk ("PXA CPU initial CCLKCFG 0x%08x\n", cclkcfg);
+      printk ("PXA CPU initial MDREFR  0x%08x\n", MDREFR);
+    }
 
-	return 0;
+    return 0;
 }
 
-static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
+static unsigned int pxa_cpufreq_get(unsigned int cpu)
 {
-	int i;
-	unsigned int freq;
+    cpumask_t cpumask_saved;
+    unsigned int cur_freq;
+
+    cpumask_saved = current->cpus_allowed;
+    set_cpus_allowed(current, cpumask_of_cpu(cpu));
+    BUG_ON(cpu != smp_processor_id());
 
-	/* try to guess pxa27x cpu */
-	if (cpu_is_pxa27x())
-		pxa27x_guess_max_freq();
-
-	/* set default policy and cpuinfo */
-	policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
-	if (cpu_is_pxa25x())
-		policy->policy = CPUFREQ_POLICY_PERFORMANCE;
-	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
-	policy->cur = get_clk_frequency_khz(0);	   /* current freq */
-	policy->min = policy->max = policy->cur;
-
-	/* Generate pxa25x the run cpufreq_frequency_table struct */
-	for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
-		pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
-		pxa255_run_freq_table[i].index = i;
-	}
-	pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-	/* Generate pxa25x the turbo cpufreq_frequency_table struct */
-	for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
-		pxa255_turbo_freq_table[i].frequency =
-			pxa255_turbo_freqs[i].khz;
-		pxa255_turbo_freq_table[i].index = i;
-	}
-	pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-	/* Generate the pxa27x cpufreq_frequency_table struct */
-	for (i = 0; i < NUM_PXA27x_FREQS; i++) {
-		freq = pxa27x_freqs[i].khz;
-		if (freq > pxa27x_maxfreq)
-			break;
-		pxa27x_freq_table[i].frequency = freq;
-		pxa27x_freq_table[i].index = i;
-	}
-	pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-	/*
-	 * Set the policy's minimum and maximum frequencies from the tables
-	 * just constructed.  This sets cpuinfo.mxx_freq, min and max.
-	 */
-	if (cpu_is_pxa25x())
-		cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table);
-	else if (cpu_is_pxa27x())
-		cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
+    cur_freq = get_clk_frequency_khz(0);
 
-	printk(KERN_INFO "PXA CPU frequency change support initialized\n");
+    set_cpus_allowed(current, cpumask_saved);
 
-	return 0;
+    return cur_freq;
 }
 
 static struct cpufreq_driver pxa_cpufreq_driver = {
-	.verify	= pxa_verify_policy,
-	.target	= pxa_set_target,
-	.init	= pxa_cpufreq_init,
-	.get	= pxa_cpufreq_get,
-	.name	= "PXA2xx",
+    .verify     = pxa_verify_policy,
+    .target     = pxa_set_target,
+    .init       = pxa_cpufreq_init,
+    .get        = pxa_cpufreq_get,
+#if defined(CONFIG_PXA25x)
+    .name       = "PXA25x",
+#elif defined(CONFIG_PXA27x)
+    .name       = "PXA27x",
+#endif
 };
 
 static int __init pxa_cpu_init(void)
 {
-	int ret = -ENODEV;
-	if (cpu_is_pxa25x() || cpu_is_pxa27x())
-		ret = cpufreq_register_driver(&pxa_cpufreq_driver);
-	return ret;
+    return cpufreq_register_driver(&pxa_cpufreq_driver);
 }
 
 static void __exit pxa_cpu_exit(void)
 {
-	cpufreq_unregister_driver(&pxa_cpufreq_driver);
+    cpufreq_unregister_driver(&pxa_cpufreq_driver);
 }
 
 
-MODULE_AUTHOR("Intrinsyc Software Inc.");
-MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
+MODULE_AUTHOR ("Intrinsyc Software Inc.");
+MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture");
 MODULE_LICENSE("GPL");
 module_init(pxa_cpu_init);
 module_exit(pxa_cpu_exit);
+
diff -urN linux-2.6.27/arch/arm/mach-pxa/include/mach/regs-lcd.h linux-2.6.27-vpac1/arch/arm/mach-pxa/include/mach/regs-lcd.h
--- linux-2.6.27/arch/arm/mach-pxa/include/mach/regs-lcd.h	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/mach-pxa/include/mach/regs-lcd.h	2008-11-27 17:19:42.000000000 +0100
@@ -43,6 +43,7 @@
 #define LCCR4_PAL_FOR_1	(1 << 15)
 #define LCCR4_PAL_FOR_2	(2 << 15)
 #define LCCR4_PAL_FOR_MASK	(3 << 15)
+#define LCCR4_PCD_DIV_MASK	(1 << 31)
 
 #define FDADR0		(0x200)	/* DMA Channel 0 Frame Descriptor Address Register */
 #define FSADR0		(0x204)	/* DMA Channel 0 Frame Source Address Register */
diff -urN linux-2.6.27/arch/arm/mach-pxa/include/mach/vpac270.h linux-2.6.27-vpac1/arch/arm/mach-pxa/include/mach/vpac270.h
--- linux-2.6.27/arch/arm/mach-pxa/include/mach/vpac270.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.27-vpac1/arch/arm/mach-pxa/include/mach/vpac270.h	2008-11-26 16:49:12.000000000 +0100
@@ -0,0 +1,253 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/vpac270.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) 2006 Voipac Technologies <support@voipac.com>
+ *
+ */
+
+#include <mach/pxa-regs.h>
+#include <mach/irqs.h>
+
+
+/*
+ * Note: include file for assembler and C
+ */
+
+/*
+ * Video settings
+ */
+
+#define VPAC270_ANALOG_VGA
+//#define VPAC270_LCD_PHILIPSLB
+
+#ifdef VPAC270_ANALOG_VGA
+/* set to 1 if you want these settings to be active */
+#define VPAC270_LCD_SETTINGS        1
+
+/* set to GPIO that switches on the backlight */
+#define VPAC270_LCD_BLO_GPIO        81
+
+/* set to 1 if the LCD is an active panel (TFT) or for VGA */
+#define VPAC270_LCD_ACTIVE          1
+
+/* set to 1 if the LCD panel is a dual-scan panel */
+#define VPAC270_LCD_DUAL            0
+
+/* set to 1 if the LCD BIAS pin should be active low (OEP) */
+#define VPAC270_BIAS_ACTIVE_LOW     0
+
+/* set to 1 if the data is sampled on the falling edge of the pixel clock PCP*/
+#define VPAC270_PIX_CLK_FALLING     0
+
+/* set to 3 if more than 16 bpp (PDFOR) */
+#define VPAC270_PIXEL_DATA_FORMAT   3
+
+/* the following settings can also be set using fbset */
+/* these are settings are for analog VGA */
+#define LCD_PIXCLOCK                    40000
+#define LCD_XRES                        640
+#define LCD_YRES                        480
+#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH	64
+#define LCD_VERTICAL_SYNC_PULSE_WIDTH	2
+#define LCD_BEGIN_OF_LINE_WAIT_COUNT	96
+#define LCD_BEGIN_FRAME_WAIT_COUNT 	    33
+#define LCD_END_OF_LINE_WAIT_COUNT	    48
+#define LCD_END_OF_FRAME_WAIT_COUNT	    10
+#define LCD_SYNC                        0
+
+
+/* VGA timings:
+pixclk 0x1801050 Hz (25MHz) = 40000ps
+640x480 18BPP
+LCD_HORIZONTAL_SYNC_PULSE_WIDTH HSPW 0x40
+LCD_BEGIN_OF_LINE_WAIT_COUNT BLW 0x60
+LCD_END_OF_LINE_WAIT_COUNT ELW 0x30
+LCD_VERTICAL_SYNC_PULSE_WIDTH VSW 0x2
+LCD_BEGIN_FRAME_WAIT_COUNT BFW 0x21
+LCD_END_OF_FRAME_WAIT_COUNT EFW 0xa
+VPAC270_PIX_CLK_FALLING PCP 0
+FB_SYNC_HOR_HIGH_ACT_LOW HSP 1
+FB_SYNC_VERT_HIGH_ACT_LOW VSP 1
+VPAC270_LCD_DUAL SDS 0
+VPAC270_LCD_ACTIVE PAS 1
+VPAC270_BIAS_ACTIVE_LOW OEP 0
+*/
+
+#elif defined VPAC270_LCD_PHILIPSLB
+
+/* set to 1 if you want these settings to be active */
+#define VPAC270_LCD_SETTINGS        1
+
+/* set to GPIO that switches on the backlight */
+#define VPAC270_LCD_BLO_GPIO        81
+
+/* set to 1 if the LCD is an active panel (TFT) or for VGA */
+#define VPAC270_LCD_ACTIVE          1
+
+/* set to 1 if the LCD panel is a dual-scan panel */
+#define VPAC270_LCD_DUAL            0
+
+/* set to 1 if the LCD BIAS pin should be active low (OEP) */
+#define VPAC270_BIAS_ACTIVE_LOW     0
+
+/* set to 1 if the data is sampled on the falling edge of the pixel clock PCP*/
+#define VPAC270_PIX_CLK_FALLING     1
+
+/* set to 3 if more than 16 bpp (PDFOR) */
+#define VPAC270_PIXEL_DATA_FORMAT   3
+
+/* the following settings can also be set using fbset */
+/* these are settings are for analog VGA */
+#define LCD_PIXCLOCK                    40000
+#define LCD_XRES                        640
+#define LCD_YRES                        480
+#define LCD_HORIZONTAL_SYNC_PULSE_WIDTH	2
+#define LCD_VERTICAL_SYNC_PULSE_WIDTH	45
+#define LCD_BEGIN_OF_LINE_WAIT_COUNT	160
+#define LCD_BEGIN_FRAME_WAIT_COUNT 	    0
+#define LCD_END_OF_LINE_WAIT_COUNT	    2
+#define LCD_END_OF_FRAME_WAIT_COUNT	    0
+#define LCD_SYNC			(FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT)
+
+/* Philips LB064V02-A1 timings:
+pixclk 0x1801050 Hz (25MHz) = 40000ps
+640x480 18BPP
+LCD_HORIZONTAL_SYNC_PULSE_WIDTH HSPW 2
+LCD_BEGIN_OF_LINE_WAIT_COUNT BLW 160
+LCD_END_OF_LINE_WAIT_COUNT ELW 2
+LCD_VERTICAL_SYNC_PULSE_WIDTH VSW 45
+LCD_BEGIN_FRAME_WAIT_COUNT BFW 0
+LCD_END_OF_FRAME_WAIT_COUNT EFW 0
+VPAC270_PIX_CLK_FALLING PCP 1
+FB_SYNC_HOR_HIGH_ACT_LOW HSP 0
+FB_SYNC_VERT_HIGH_ACT_LOW VSP 0
+VPAC270_LCD_DUAL SDS 0
+VPAC270_LCD_ACTIVE PAS 1
+VPAC270_BIAS_ACTIVE_LOW OEP 0
+*/
+#endif
+
+
+/*
+ * physical memory map
+ */
+
+#define VPAC270_FLASH_PHYS		PXA_CS0_PHYS    /* 0x00000000 */
+#define VPAC270_FLASH_SIZE		(0x02000000)
+
+#define VPAC270_ETH_PHYS		PXA_CS2_PHYS    /* 0x08000000 */
+//#define VPAC270_CPLD_PHYS       PXA_CS3_PHYS    /* 0x0c000000 */
+#define VPAC270_BCR_PHYS        0x0e000000
+
+/*
+ * virtual memory map
+ */
+
+#define VPAC270_FLASH           0x00000000
+//#define VPAC270_ETH_BASE		0xf4000000
+#define VPAC270_ETH_SIZE	8
+
+//#define VPAC270_CPLD_BASE       0xf0000000
+//#define VPAC270_CPLD_SIZE       0x04000000
+#define VPAC270_CF_OFFSET	    0x00000000
+#define VPAC270_BCR_OFFSET	    0x02000000
+#define VPAC270_IRDA_OFFSET	    0x02400000
+#define VPAC270_UPS_OFFSET	    0x02800000
+#define VPAC270_DCR_OFFSET	    0x03800000
+
+//#ifndef __ASSEMBLY__
+//#  define CPLD_REG(x)           (*((volatile unsigned short *)(VPAC270_CPLD_BASE + (x))))
+//#else
+//#  define CPLD_REG(x)           (VPAC270_CPLD_BASE + (x))
+//#endif
+
+
+//#define DM9000_BASE		        VPAC270_ETH_BASE
+//#define DM9000_MMIO             1
+//#define DM9000_ADDRFROMTAG      1
+
+#define VPAC270_CF0_STATUS      CPLD_REG(VPAC270_CF_OFFSET)
+#define VPAC270_BCR_CONTROL     CPLD_REG(VPAC270_BCR_OFFSET)
+#define VPAC270_DCR             CPLD_REG(VPAC270_DCR_OFFSET)
+
+/*
+ * interrupts
+ */
+/* Ethernet */
+#define GPIO_ETH_IRQ    114
+#define VPAC270_ETH_IRQ IRQ_GPIO(GPIO_ETH_IRQ)
+#define DM9000_IRQ      VPAC270_ETH_IRQ
+
+/* IDE */
+#define GPIO_IDE_IRQ	36
+#define VPAC270_IDE_IRQ IRQ_GPIO(GPIO_IDE_IRQ)
+
+/* Compact Flash/PCMCIA */
+#define GPIO_PCMCIA0_CD_IRQ     84
+#define VPAC270_PCMCIA0_CD_IRQ  IRQ_GPIO(GPIO_PCMCIA0_CD_IRQ)
+#define GPIO_PCMCIA1_CD_IRQ     17
+#define VPAC270_PCMCIA1_CD_IRQ  IRQ_GPIO(GPIO_PCMCIA1_CD_IRQ)
+#define VPAC270_PCMCIA_CD_EDGE  IRQ_TYPE_EDGE_BOTH
+#define GPIO_PCMCIA0_RDY_IRQ    35
+#define VPAC270_PCMCIA0_RDY_IRQ IRQ_GPIO(GPIO_PCMCIA0_RDY_IRQ)
+#define GPIO_PCMCIA1_RDY_IRQ    12
+#define VPAC270_PCMCIA1_RDY_IRQ IRQ_GPIO(GPIO_PCMCIA1_RDY_IRQ)
+#define VPAC270_PCMCIA_RDY_EDGE IRQ_TYPE_EDGE_FALLING
+#define GPIO_PCMCIA_POW_EN      107
+#define GPIO_PCMCIA_NPOE        48
+#define GPIO_PCMCIA_NPOE_AF     GPIO_ALT_FN_2_OUT
+#define GPIO_PCMCIA_NPIOR       50
+#define GPIO_PCMCIA_NPIOR_AF    GPIO_ALT_FN_2_OUT
+#define GPIO_PCMCIA_NPIOW       51
+#define GPIO_PCMCIA_NPIOW_AF    GPIO_ALT_FN_2_OUT
+#define GPIO_PCMCIA_NPCE1       85
+#define GPIO_PCMCIA_NPCE1_AF    GPIO_ALT_FN_1_OUT
+#define GPIO_PCMCIA_NPCE2       54
+#define GPIO_PCMCIA_NPCE2_AF    GPIO_ALT_FN_2_OUT
+#define GPIO_PCMCIA_NPREG       55
+#define GPIO_PCMCIA_NPREG_AF    GPIO_ALT_FN_2_OUT
+#define GPIO_PCMCIA_NPWAIT      56
+#define GPIO_PCMCIA_NPWAIT_AF   GPIO_ALT_FN_1_IN
+#define GPIO_PCMCIA_NPIOIS16    57
+#define GPIO_PCMCIA_NPIOIS16_AF GPIO_ALT_FN_1_IN
+#define GPIO_PCMCIA_PSKTSEL     104
+#define GPIO_PCMCIA_PSKTSEL_AF  GPIO_ALT_FN_1_OUT
+#define GPIO_PCMCIA0_RESET      11
+#define GPIO_PCMCIA1_RESET      16
+//#define GPIO_PCMCIA0_BVD1       83
+//#define GPIO_PCMCIA0_BVD2       82
+
+#define PCC0_DETECT (GPLR(GPIO_PCMCIA0_CD_IRQ) & GPIO_bit(GPIO_PCMCIA0_CD_IRQ))
+#define PCC0_READY (GPLR(GPIO_PCMCIA0_RDY_IRQ) & GPIO_bit(GPIO_PCMCIA0_RDY_IRQ))
+#define PCC1_DETECT (GPLR(GPIO_PCMCIA1_CD_IRQ) & GPIO_bit(GPIO_PCMCIA1_CD_IRQ))
+#define PCC1_READY (GPLR(GPIO_PCMCIA1_RDY_IRQ) & GPIO_bit(GPIO_PCMCIA1_RDY_IRQ))
+#define PCC_BVD1()  (GPLR(GPIO_PCMCIA0_BVD1) & GPIO_bit(GPIO_PCMCIA0_BVD1))
+#define PCC_BVD2()  (GPLR(GPIO_PCMCIA0_BVD2) & GPIO_bit(GPIO_PCMCIA0_BVD2))
+#define PCC_VS3V()  1       /* only 3.3V supported */
+#define PCC_VS5V()  0       /* only 3.3V supported */
+#define PCC_PWR_ON() (GPCR(GPIO_PCMCIA_POW_EN) |= GPIO_bit(GPIO_PCMCIA_POW_EN))
+#define PCC_PWR_OFF() (GPSR(GPIO_PCMCIA_POW_EN) |= GPIO_bit(GPIO_PCMCIA_POW_EN))
+
+/* MMC/SD */
+#define GPIO_MMC_CD_IRQ         53
+#define VPAC270_MMC_CD_IRQ      IRQ_GPIO(GPIO_MMC_CD_IRQ)
+#define GPIO_MMCCLK_AF          GPIO32_MMCCLK_MD
+#define GPIO_MMCDAT0_AF          GPIO92_MMCDAT0
+#define GPIO_MMCDAT1_AF          GPIO109_MMCDAT1
+#define GPIO_MMCDAT2_AF          GPIO110_MMCDAT2
+#define GPIO_MMCDAT3_AF          GPIO111_MMCDAT3
+#define GPIO_MMCCMD_AF          GPIO112_MMCCMD_MD
+#define GPIO_MMCCS0_AF          GPIO110_MMCCS0_MD
+
+/* TouchScreen and Sound */
+#define GPIO_TOUCH_IRQ          113
+#define VPAC270_TOUCH_IRQ       IRQ_GPIO(GPIO_TOUCH_IRQ)
+
+#define GPIO_AC97_RESET         95
+#define GPIO_AC97_RST_AF        GPIO_ALT_FN_1_OUT
+#define GPIO_AC97_SYSCLK        98
+#define GPIO_AC97_SYSCLK_AF     GPIO_ALT_FN_1_OUT
diff -urN linux-2.6.27/arch/arm/mach-pxa/Kconfig linux-2.6.27-vpac1/arch/arm/mach-pxa/Kconfig
--- linux-2.6.27/arch/arm/mach-pxa/Kconfig	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/mach-pxa/Kconfig	2008-11-26 10:49:43.000000000 +0100
@@ -49,6 +49,11 @@
 	select PXA27x
 	select HAVE_PWM
 
+config MACH_VPAC270
+	bool "Voipac PXA270 Module"
+	select PXA27x
+	select IWMMXT
+
 config ARCH_PXA_IDP
 	bool "Accelent Xscale IDP"
 	select PXA25x
diff -urN linux-2.6.27/arch/arm/mach-pxa/Makefile linux-2.6.27-vpac1/arch/arm/mach-pxa/Makefile
--- linux-2.6.27/arch/arm/mach-pxa/Makefile	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/mach-pxa/Makefile	2008-11-26 10:50:38.000000000 +0100
@@ -35,6 +35,7 @@
 obj-$(CONFIG_MACH_PCM027)	+= pcm027.o
 obj-$(CONFIG_MACH_PCM990_BASEBOARD)	+= pcm990-baseboard.o
 obj-$(CONFIG_MACH_TOSA)		+= tosa.o
+obj-$(CONFIG_MACH_VPAC270)	+= vpac270.o
 obj-$(CONFIG_MACH_EM_X270)	+= em-x270.o
 obj-$(CONFIG_MACH_MAGICIAN)	+= magician.o
 obj-$(CONFIG_ARCH_PXA_ESERIES)	+= eseries.o eseries_udc.o
diff -urN linux-2.6.27/arch/arm/mach-pxa/vpac270.c linux-2.6.27-vpac1/arch/arm/mach-pxa/vpac270.c
--- linux-2.6.27/arch/arm/mach-pxa/vpac270.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.27-vpac1/arch/arm/mach-pxa/vpac270.c	2009-01-02 14:48:59.000000000 +0100
@@ -0,0 +1,549 @@
+ /*
+ *  linux/arch/arm/mach-pxa/vpac270.c
+ *
+ *  Support for Voipac PXA270 module
+ *
+ *  Copyright (c) 2006 Voipac Technologies <support@voipac.com>
+ *  
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/bitops.h>
+#include <linux/fb.h>
+#include <linux/ioport.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/flash.h>
+
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/pxa2xx-regs.h>
+#include <mach/vpac270.h>
+#include <mach/pxa2xx_spi.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
+#include <mach/mmc.h>
+#include <mach/i2c.h>
+#include <mach/irda.h>
+#include <mach/ohci.h>
+#include <mach/udc.h>
+#include <mach/pxa27x-udc.h>
+#include <mach/pxa2xx-gpio.h>
+//#include <mach/mfp-pxa27x.h>
+
+#include "generic.h"
+
+#include <linux/dm9000.h>
+
+#define GPIO100_FFCTS_MD        (100 | GPIO_ALT_FN_2_IN)
+#define GPIO10_FFDCD_MD         (10 | GPIO_ALT_FN_1_IN)
+#define GPIO33_FFDSR_MD         (33 | GPIO_ALT_FN_2_IN)
+#define GPIO27_FFRTS_MD         (27 | GPIO_ALT_FN_3_OUT)
+
+static void __init vpac270_init_irq(void)
+{
+	pxa27x_init_irq();
+
+	/* setup extra vpac270 irqs */
+	set_irq_type(VPAC270_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
+	set_irq_type(VPAC270_IDE_IRQ, IRQ_TYPE_EDGE_RISING);
+}
+
+#ifdef CONFIG_DM9000
+#define DM9000_PHYS_BASE (VPAC270_ETH_PHYS + 0x300)
+static struct resource dm9000_resources[] = {
+        [0] = {
+                .start = DM9000_PHYS_BASE,
+                .end   = DM9000_PHYS_BASE + 3,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = DM9000_PHYS_BASE + 4,
+                .end   = DM9000_PHYS_BASE + 4 + 0x3f,
+                .flags = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start = (VPAC270_ETH_IRQ),
+                .end   = (VPAC270_ETH_IRQ),
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+        }
+};
+
+static struct dm9000_plat_data dm9000_setup = {
+        .flags          = DM9000_PLATF_32BITONLY,
+};
+
+static struct platform_device dm9000_device = {
+    .name           = "dm9000",
+    .id             = 0,
+    .num_resources  = ARRAY_SIZE(dm9000_resources),
+    .resource       = dm9000_resources,
+    .dev            = {
+        .platform_data = &dm9000_setup,
+    }
+};
+#endif
+
+#ifdef CONFIG_SPI_PXA2XX
+static struct resource pxa_ssp_resources[] = {
+        [0] = {
+                .start  = __PREG(SSCR0_P(1)),
+                .end    = __PREG(SSCR0_P(1)) + 0x14,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_SSP,
+                .end    = IRQ_SSP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct pxa2xx_spi_master pxa_ssp_master_info = {
+        .ssp_type       = PXA25x_SSP,
+        .clock_enable   = CKEN_SSP,
+        .num_chipselect = 1,
+};
+
+static struct platform_device vpac270_ssp_device = {
+        .name           = "pxa2xx-spi",
+        .id             = 1,
+        .resource       = pxa_ssp_resources,
+        .num_resources  = ARRAY_SIZE(pxa_ssp_resources),
+        .dev = {
+                .platform_data  = &pxa_ssp_master_info,
+        },
+};
+#endif
+
+#ifdef CONFIG_SND_PXA2XX_AC97
+static struct platform_device pxa_audio_device = {
+	.name           = "pxa2xx-ac97",
+	.id             = -1,
+};
+#endif
+
+#ifdef CONFIG_LEDS_VPAC270
+static struct platform_device vpac270led_device = {
+	.name		= "vpac270-led",
+	.id		= -1,
+};
+#endif
+
+#ifdef CONFIG_MTD_ONENAND_PXA27x
+
+#define GPIO_ONENAND_IRQ	116
+#define VPAC270_ONENAND_IRQ	IRQ_GPIO(GPIO_ONENAND_IRQ)
+
+static struct resource vpac270onenand_resources[] = {
+        [0] = {
+                .start  = PXA_CS0_PHYS,
+                .end    = (PXA_CS0_PHYS + SZ_128K - 1),
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = VPAC270_ONENAND_IRQ,
+                .end    = VPAC270_ONENAND_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct mtd_partition vpac270onenand_partitions[] = {
+        {
+                name:           "Bootloader",
+                size:           0x00020000, /* 128kB u-boot and config params */
+                offset:         0,
+                /*mask_flags:   MTD_WRITEABLE   force read-only */
+        },{
+                name:           "Kernel",
+                size:           0x00140000, /* 1MB for kernel */
+                offset:         MTDPART_OFS_APPEND,
+        },{
+                name:           "Filesystem",   /* the rest for filesystem */
+                size:           MTDPART_SIZ_FULL,
+                offset:         MTDPART_OFS_APPEND
+        }
+};
+
+static struct flash_platform_data vpac270onenand_data = {
+	.parts          = vpac270onenand_partitions,
+	.nr_parts       = ARRAY_SIZE(vpac270onenand_partitions),
+};
+
+static struct platform_device vpac270onenand_device = {
+	.name		= "onenand",
+	.id		= 0,
+	.dev = {
+		.platform_data = &vpac270onenand_data,
+	},
+	.resource = vpac270onenand_resources,
+	.num_resources = ARRAY_SIZE(vpac270onenand_resources),
+};
+#endif
+
+#ifdef CONFIG_MTD_CFI
+static struct resource vpac270nor_resources = {
+                .start  = PXA_CS0_PHYS,
+                .end    = PXA_CS0_PHYS + SZ_64M - 1,
+                .flags  = IORESOURCE_MEM,
+};
+
+static struct mtd_partition vpac270nor_partitions[] = {
+	{
+                name:           "Bootloader",
+                size:           0x00020000, /* 128kB u-boot and config params */
+                offset:         0,
+                /*mask_flags:   MTD_WRITEABLE   force read-only */
+        },{
+                name:           "Kernel",
+                size:           0x00140000, /* 1MB for kernel */
+                offset:         MTDPART_OFS_APPEND,
+        },{
+                name:           "Filesystem",   /* the rest for filesystem */
+                size:           MTDPART_SIZ_FULL,
+                offset:         MTDPART_OFS_APPEND
+        }
+};
+
+static struct flash_platform_data vpac270nor_data = {
+		.name		= "vpac270dimm",
+                .map_name       = "cfi_probe",
+                .parts          = vpac270nor_partitions,
+                .nr_parts       = ARRAY_SIZE(vpac270nor_partitions),
+		.width          = 2,
+};
+
+static struct platform_device vpac270nor_device = {
+                .name           = "pxa2xx-flash",
+                .id             = 0,
+                .dev = {
+                        .platform_data = &vpac270nor_data,
+                },
+		.resource = &vpac270nor_resources,
+		.num_resources = 1,
+};
+#endif
+
+static struct platform_device *devices[] __initdata = {
+#ifdef CONFIG_DM9000
+	&dm9000_device,
+#endif
+#ifdef CONFIG_SND_PXA2XX_AC97
+	&pxa_audio_device,
+#endif
+#ifdef CONFIG_SPI_PXA2XX
+	&vpac270_ssp_device,
+#endif
+#ifdef CONFIG_SERIO_VPAC270
+	&vpac270ms_device,
+	&vpac270kb_device,
+#endif
+#ifdef CONFIG_LEDS_VPAC270
+    	&vpac270led_device,
+#endif
+#ifdef CONFIG_MTD_ONENAND_PXA27x
+	&vpac270onenand_device,
+#endif
+#ifdef CONFIG_MTD_CFI
+	&vpac270nor_device,
+#endif
+};
+
+/*
+ * MMC/SD Device
+ *
+ */
+static struct pxamci_platform_data vpac270_mci_platform_data;
+
+static int vpac270_mci_init(struct device *dev, irqreturn_t (*detect_int)(int, void *), void *data)
+{
+    int err;
+
+    printk("Voipac PXA270 MMC/SD setup ");
+	/* setup GPIO for PXA2xx MMC controller	*/
+	pxa_gpio_mode(GPIO32_MMCCLK_MD);
+	pxa_gpio_mode(GPIO112_MMCCMD_MD);
+	pxa_gpio_mode(GPIO92_MMCDAT0_MD);
+	pxa_gpio_mode(GPIO109_MMCDAT1_MD);
+	pxa_gpio_mode(GPIO110_MMCDAT2_MD);
+	pxa_gpio_mode(GPIO111_MMCDAT3_MD);
+
+	pxa_gpio_mode(GPIO_MMC_CD_IRQ);
+
+        vpac270_mci_platform_data.detect_delay = msecs_to_jiffies(250);
+
+	err = request_irq(VPAC270_MMC_CD_IRQ, detect_int, 0,
+			     "MMC card detect", data);
+	if (err) {
+		printk(KERN_ERR "vpac270_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
+		return -1;
+	}
+
+	set_irq_type(VPAC270_MMC_CD_IRQ, IRQ_TYPE_EDGE_BOTH);
+
+    printk("done.\n");
+	return 0;
+}
+
+static struct pxamci_platform_data vpac270_mci_platform_data = {
+	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
+	.init 		= vpac270_mci_init,
+};
+
+#ifdef CONFIG_FB_PXA
+
+#ifdef CONFIG_FB_PXA_BPP8
+#define FB_PXA_BPP 8
+#else
+#define FB_PXA_BPP 16
+#endif
+
+static struct pxafb_mode_info  vpac270_fb_mode_info[] __initdata = {
+#if defined(CONFIG_FB_PXA_TX14D14VM1BBA)
+/*	VGA 640x480 18bit, pclk=26MHz	*/
+{
+        .pixclock               = 57693,	// PCD=3
+        .xres                   = 640,
+        .yres                   = 480,
+        .bpp                    = 8,
+        .hsync_len              = 32,
+        .left_margin            = 144,
+        .right_margin           = 32,
+        .vsync_len              = 2,
+        .upper_margin           = 13,
+        .lower_margin           = 30,
+        .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
+},
+#elif defined(CONFIG_FB_PXA_FG0700A0DSSWAGT1)
+/*	WIDE SVGA 800x480 16bit, pclk=34.6MHz	*/
+{
+        .pixclock               = 38462,	// PCD=2
+        .xres                   = 800,
+        .yres                   = 480,
+        .bpp                    = FB_PXA_BPP,
+        .hsync_len              = 8,
+        .left_margin            = 128,
+        .right_margin           = 48,
+        .vsync_len              = 1,
+        .upper_margin           = 33,
+        .lower_margin           = 1,
+        .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
+},
+#elif defined(CONFIG_FB_PXA_VGA)
+/*	VGA 640x480 16bit, pclk=26MHz	*/
+{
+        .pixclock               = 57693,	// PCD=3
+        .xres                   = 640,
+        .yres                   = 480,
+        .bpp                    = FB_PXA_BPP,
+        .hsync_len              = 64,
+        .left_margin            = 96,
+        .right_margin           = 48,
+        .vsync_len              = 2,
+        .upper_margin           = 33,
+        .lower_margin           = 10,
+        .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
+},
+#elif defined(CONFIG_FB_PXA_SVGA)
+/*	SVGA 800x600 16bit, pclk=34.6MHz	*/
+{
+        .pixclock               = 38462,	// PCD=2
+        .xres                   = 800,
+        .yres                   = 600,
+        .bpp                    = FB_PXA_BPP,
+        .hsync_len              = 8,
+        .left_margin            = 128,
+        .right_margin           = 48,
+        .vsync_len              = 1,
+        .upper_margin           = 33,
+        .lower_margin           = 1,
+        .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
+},
+#elif defined(CONFIG_FB_PXA_XGA)
+/*	XGA 1024x768 16bit, pclk=52.0MHz	*/
+{
+        .pixclock               = 19231,	// PCD=1
+        .xres                   = 1024,
+        .yres                   = 768,
+        .bpp                    = FB_PXA_BPP,
+        .hsync_len              = 63,
+        .left_margin            = 220,
+        .right_margin           = 8,
+        .vsync_len              = 1,
+        .upper_margin           = 33,
+        .lower_margin           = 2,
+        .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
+},
+#endif
+};
+
+static struct pxafb_mach_info vpac270_fb_mach_info __initdata = {
+	.modes			= vpac270_fb_mode_info,
+	.num_modes		= ARRAY_SIZE(vpac270_fb_mode_info),
+        .lccr0                  = 0x043008f8,
+        .lccr3                  = 0x0040ff00,
+#if defined(CONFIG_FB_PXA_TX14D14VM1BBA)
+	.lccr4			= 0x80000000 | LCCR4_PAL_FOR_2,
+#else
+	.lccr4			= 0x80000000 | LCCR4_PAL_FOR_0,
+#endif
+};
+#endif	// CONFIG_FB_PXA
+
+static int vpac270_ohci_init(struct device *dev)
+{
+        /* setup Port1 GPIO pin. */
+        pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);  /* USBHPWR1 */
+        pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
+	pxa_gpio_mode(119 | GPIO_ALT_FN_1_IN);
+    	pxa_gpio_mode(120 | GPIO_ALT_FN_2_OUT);
+
+        /* Set the Power Control Polarity Low and Power Sense
+           Polarity Low to active low. */
+        UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+                ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
+
+	UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
+
+        return 0;
+}
+
+static struct pxaohci_platform_data vpac270_ohci_platform_data = {
+        .port_mode      = PMM_GLOBAL_MODE,	//PMM_PERPORT_MODE, PMM_NPS_MODE,
+        .init           = vpac270_ohci_init,
+};
+
+/* USB Device Controller */
+static void vpac270_udc_enable(int cmd) 
+{
+	switch (cmd)
+	{
+		case PXA2XX_UDC_CMD_DISCONNECT:
+			printk (KERN_NOTICE "VPAC270 UDC cmd disconnect\n");
+
+			UP2OCR = (UP2OCR | UP2OCR_HXS| UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE) &
+				~(UP2OCR_DPPUE | UP2OCR_DMPUE | UP2OCR_DPPUBE | UP2OCR_DMPUBE);
+			break;
+
+		case PXA2XX_UDC_CMD_CONNECT:
+			printk (KERN_NOTICE "VPAC270 UDC cmd connect\n");
+
+			UP2OCR = (UP2OCR | UP2OCR_HXOE | UP2OCR_DPPUE) &
+				~(UP2OCR_HXS | UP2OCR_DMPUE | UP2OCR_DPPUBE |
+				 UP2OCR_DMPUBE | UP2OCR_DPPDE | UP2OCR_DMPDE);
+			break;
+	}
+}
+
+static struct pxa2xx_udc_mach_info vpac270_udc_mach_info = {
+	.udc_command      = vpac270_udc_enable,
+};
+
+static struct i2c_board_info __initdata vpac270_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("rtc-ds1307", 0x68),
+		.type   = "ds1339",
+	}
+};
+
+static void __init vpac270_init(void)
+{
+    /* reset UCB1400 */
+    GPSR2 &= ~(1u << 31);
+    pxa_gpio_mode(GPIO_AC97_RESET | GPIO_OUT);
+    udelay(12);
+    pxa_set_mci_info(&vpac270_mci_platform_data);
+    platform_add_devices(devices, ARRAY_SIZE(devices));
+    pxa_set_i2c_info(NULL);
+    i2c_register_board_info(0, vpac270_i2c_devices, ARRAY_SIZE(vpac270_i2c_devices));
+#ifdef CONFIG_FB_PXA
+    set_pxa_fb_info(&vpac270_fb_mach_info);
+#if defined(CONFIG_FB_PXA_TX14D14VM1BBA)
+    pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
+    pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
+#endif
+#endif
+    pxa_set_ohci_info(&vpac270_ohci_platform_data);
+    pxa_set_udc_info( &vpac270_udc_mach_info );
+
+    GPDR(VPAC270_LCD_BLO_GPIO) |= GPIO_bit(VPAC270_LCD_BLO_GPIO);
+    GPSR(VPAC270_LCD_BLO_GPIO) |= GPIO_bit(VPAC270_LCD_BLO_GPIO);
+
+}
+
+static struct map_desc vpac270_io_desc[] __initdata = {
+ /* virtual         physical            length              type */
+/*{ VPAC270_FLASH,  VPAC270_FLASH_PHYS, VPAC270_FLASH_SIZE, MT_DEVICE },
+  { VPAC270_ETH_BASE, VPAC270_ETH_PHYS, VPAC270_ETH_SIZE,   MT_DEVICE },*/
+//  { 0xf0000000, __phys_to_pfn(0x0c000000), 0x04000000, MT_DEVICE },
+};
+
+static void __init vpac270_map_io(void)
+{
+	pxa_map_io();
+	iotable_init(vpac270_io_desc, ARRAY_SIZE(vpac270_io_desc));
+
+	/* enabling FFUART */
+	CKEN |= CKEN_FFUART;
+	pxa_gpio_mode(GPIO34_FFRXD_MD);
+	pxa_gpio_mode(GPIO100_FFCTS_MD);
+	pxa_gpio_mode(GPIO10_FFDCD_MD);
+	pxa_gpio_mode(GPIO33_FFDSR_MD);
+	pxa_gpio_mode(GPIO38_FFRI_MD);
+	pxa_gpio_mode(GPIO39_FFTXD_MD);
+	pxa_gpio_mode(GPIO40_FFDTR_MD);
+	pxa_gpio_mode(GPIO27_FFRTS_MD);
+
+	/* enabling BTUART */
+	CKEN |= CKEN_BTUART;
+	pxa_gpio_mode(GPIO42_BTRXD_MD);
+	pxa_gpio_mode(GPIO43_BTTXD_MD);
+	pxa_gpio_mode(GPIO44_BTCTS_MD);
+	pxa_gpio_mode(GPIO45_BTRTS_MD);
+
+	/* This is for the Davicom chip select */
+	pxa_gpio_mode(GPIO78_nCS_2_MD);
+
+	/* bring hdd out of reset */
+	GPCR(GPIO_PCMCIA1_RESET) |= GPIO_bit(GPIO_PCMCIA1_RESET);       // disable reset
+
+	/* setup sleep mode values */
+	PWER  = 0x00000002;
+	PFER  = 0x00000000;
+	PRER  = 0x00000002;
+	PGSR0 = 0x00008000;
+	PGSR1 = 0x003F0202;
+	PGSR2 = 0x0001C000;
+	PCFR |= PCFR_OPDE;
+}
+
+MACHINE_START(VPAC270, "Voipac PXA270 Module")
+        /* Maintainer: Voipac Technologies <support@voipac.com> */
+        .phys_io        = 0x40000000,
+        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= (PHYS_OFFSET + 0x100),
+        .map_io         = vpac270_map_io,
+        .init_irq       = vpac270_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = vpac270_init,
+MACHINE_END
+
diff -urN linux-2.6.27/arch/arm/Makefile linux-2.6.27-vpac1/arch/arm/Makefile
--- linux-2.6.27/arch/arm/Makefile	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/arch/arm/Makefile	2008-11-26 11:09:39.000000000 +0100
@@ -20,7 +20,7 @@
 
 # Do not use arch/arm/defconfig - it's always outdated.
 # Select a platform tht is kept up-to-date
-KBUILD_DEFCONFIG := versatile_defconfig
+KBUILD_DEFCONFIG := vpac270_defconfig
 
 # defines filename extension depending memory manement type.
 ifeq ($(CONFIG_MMU),)
diff -urN linux-2.6.27/drivers/cpufreq/Kconfig linux-2.6.27-vpac1/drivers/cpufreq/Kconfig
--- linux-2.6.27/drivers/cpufreq/Kconfig	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/cpufreq/Kconfig	2008-11-26 13:07:57.000000000 +0100
@@ -16,7 +16,7 @@
 if CPU_FREQ
 
 config CPU_FREQ_TABLE
-	tristate
+	def_tristate y
 
 config CPU_FREQ_DEBUG
 	bool "Enable CPUfreq debugging"
diff -urN linux-2.6.27/drivers/ide/arm/Makefile linux-2.6.27-vpac1/drivers/ide/arm/Makefile
--- linux-2.6.27/drivers/ide/arm/Makefile	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/ide/arm/Makefile	2008-11-26 11:29:07.000000000 +0100
@@ -2,6 +2,7 @@
 obj-$(CONFIG_BLK_DEV_IDE_ICSIDE)	+= icside.o
 obj-$(CONFIG_BLK_DEV_IDE_RAPIDE)	+= rapide.o
 obj-$(CONFIG_BLK_DEV_PALMCHIP_BK3710)	+= palm_bk3710.o
+obj-$(CONFIG_BLK_DEV_IDE_VPAC270)	+= vpac270-ide.o
 
 ifeq ($(CONFIG_IDE_ARM), m)
 	obj-m += ide_arm.o
diff -urN linux-2.6.27/drivers/ide/arm/vpac270-ide.c linux-2.6.27-vpac1/drivers/ide/arm/vpac270-ide.c
--- linux-2.6.27/drivers/ide/arm/vpac270-ide.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.27-vpac1/drivers/ide/arm/vpac270-ide.c	2008-12-11 17:53:08.000000000 +0100
@@ -0,0 +1,282 @@
+/* linux/drivers/ide/arm/vpac270-ide.c
+ *
+ * Copyright (c) 2006 Voipac Technologies <support@voipac.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+//#include <linux/config.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/blkdev.h>
+#include <linux/errno.h>
+#include <linux/hdreg.h>
+#include <linux/ide.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/scatterlist.h>
+
+#include <asm/dma.h>
+#include <asm/io.h>
+
+#include <mach/vpac270.h>
+
+#define DRQSR1            __REG(0x400000e4)  /* DMA Request Status Register 1 */
+#define DRQSR_REQCLR      (1 << 8)        /* Clear Pending Requests */
+
+#define IDE_BASE_PHYS	0x0c000000
+//#define DMA_IRQ_DETECT IRQ_GPIO(80)
+
+#define GPIO_ALT_FN_1_IN       0x100
+#define GPIO80_DREQ_1_MD         (80 | GPIO_ALT_FN_1_IN)
+
+static void vpac270_set_dma_mode(ide_drive_t *drive, const u8 xfer_mode)
+{
+        int cycle_time = 0, use_dma_info = 0;
+
+        switch (xfer_mode) {
+        case XFER_MW_DMA_2:
+                cycle_time = 120;
+                use_dma_info = 1;
+                break;
+
+        case XFER_MW_DMA_1:
+                cycle_time = 250;
+                use_dma_info = 1;
+                break;
+
+        case XFER_MW_DMA_0:
+                cycle_time = 480;
+                break;
+
+        case XFER_SW_DMA_2:
+        case XFER_SW_DMA_1:
+        case XFER_SW_DMA_0:
+                cycle_time = 480;
+                break;
+        }
+
+        if (use_dma_info && drive->id->eide_dma_time > cycle_time)
+                cycle_time = drive->id->eide_dma_time;
+
+        drive->drive_data = cycle_time;
+
+        printk("%s: %s selected (peak %dMB/s)\n", drive->name,
+                ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
+}
+
+static int vpac270_dma_setup(ide_drive_t *drive)
+{
+        ide_hwif_t *hwif = HWIF(drive);
+        struct request *rq = hwif->hwgroup->rq;
+	
+	blk_queue_max_segment_size( drive->queue, (DCMD_LENGTH & 0xfffffe00) );
+	ide_map_sg(drive, rq);
+
+        hwif->sg_dma_direction = (rq_data_dir(rq) == READ)?
+				DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+	if( hwif->sg_nents > 0)
+	{
+		int i = 0;
+		int dma = hwif->dma;
+		struct scatterlist *sg = hwif->sg_table;
+
+		pxa_dma_desc *ddadr = (void *) hwif->dmatable_dma;
+		pxa_dma_desc *ddptr = (void *) hwif->dmatable_cpu;
+
+		DCSR(dma) = 0;
+		
+		do
+		{
+        	        u32 length = sg->length;
+
+			sg->dma_address = dma_map_page( NULL, sg_page(sg), sg->offset,
+					length, hwif->sg_dma_direction);
+			
+			ddptr->ddadr = (u32) ++ddadr;	// next DDADR
+
+			if(hwif->sg_dma_direction == DMA_FROM_DEVICE)
+			{
+				ddptr->dsadr = 0xc000020;	// DSADR
+				ddptr->dtadr = sg->dma_address;	// DTADR
+				ddptr->dcmd = (DCMD_INCTRGADDR | DCMD_BURST32 | DCMD_FLOWSRC |
+						DCMD_WIDTH2 | (DCMD_LENGTH & length));
+			}
+			else
+			{
+				ddptr->dsadr = sg->dma_address;	// DSADR
+				ddptr->dtadr = 0xc000020;	// DTADR
+				ddptr->dcmd = (DCMD_INCSRCADDR | DCMD_BURST32 | DCMD_FLOWTRG |
+						DCMD_WIDTH2 | (DCMD_LENGTH & length));
+			}
+			sg++;
+		}
+		while( ++i < hwif->sg_nents && ddptr++);
+
+		ddptr->ddadr = DDADR_STOP;
+
+		DDADR(dma) = hwif->dmatable_dma;
+
+		DRQSR1 = DRQSR_REQCLR;
+		DRCMR1 = dma | DRCMR_MAPVLD;
+	        
+		DCSR(dma) = DCSR_RUN;
+        	drive->waiting_for_dma = 1;
+	}
+        return 0;
+}
+
+static void vpac270_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
+{
+	ide_execute_command(drive, cmd, &ide_dma_intr, 2 * WAIT_CMD, NULL);
+}
+
+static void vpac270_dma_start(ide_drive_t *drive)
+{
+}
+
+static int vpac270_dma_end(ide_drive_t *drive)
+{
+        ide_hwif_t *hwif = HWIF(drive);
+        int dma = hwif->dma;
+	
+	drive->waiting_for_dma = 0;
+
+	while (!(DCSR(dma) & DCSR_STOPSTATE))
+		cpu_relax();
+	DCSR(dma) = 0;
+
+	dma_unmap_sg( NULL, hwif->sg_table, hwif->sg_nents,
+			hwif->sg_dma_direction);
+	return 0;
+}
+
+static int vpac270_dma_test_irq(ide_drive_t *drive)
+{
+	return (GPLR(GPIO_IDE_IRQ) & GPIO_bit(GPIO_IDE_IRQ));
+}
+
+static void vpac270_dma_timeout(ide_drive_t *drive)
+{
+        ide_hwif_t *hwif = HWIF(drive);
+        int dma = hwif->dma;
+printk("%s:%d\n",__FUNCTION__,__LINE__);
+printk("%s:%d DCSR(%d)=%08x\n",__FUNCTION__,__LINE__,dma,DCSR(dma));
+        printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
+
+        if (vpac270_dma_test_irq(drive))
+                return;
+
+	ide_dump_status(drive, "DMA timeout", hwif->tp_ops->read_status(hwif));
+
+        vpac270_dma_end(drive);
+}
+
+static void vpac270_dma_lost_irq(ide_drive_t *drive)
+{
+printk("%s:%d\n",__FUNCTION__,__LINE__);
+        printk(KERN_ERR "%s: IRQ lost\n", drive->name);
+}
+
+static void vpac270_pxa_dma_irq(int dma, void *dummy)
+{
+printk("%s:%d DCSR(%d)=%08x\n",__FUNCTION__,__LINE__,dma,DCSR(dma));
+printk("%s:%d DRQSR1=0x%08x\n",__FUNCTION__,__LINE__,DRQSR1);
+
+	DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
+}
+
+static void vpac270_dma_host_set(ide_drive_t *drive, int on)
+{
+}
+
+static int vpac270_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *port)
+{
+        printk("    %s: SG-DMA", hwif->name);
+
+	pxa_gpio_mode(GPIO80_DREQ_1_MD);
+
+	hwif->dma      = pxa_request_dma( hwif->name, DMA_PRIO_LOW,
+						vpac270_pxa_dma_irq, NULL);
+
+	hwif->dmatable_cpu = dma_alloc_coherent( NULL, (PRD_ENTRIES * 4 * sizeof(u32)),
+							&hwif->dmatable_dma, GFP_ATOMIC);
+	
+        printk(" capable, dma=%d\n", hwif->dma);
+
+	return 0;
+}
+
+static const struct ide_dma_ops vpac270_dma_ops = {
+        .dma_host_set           = vpac270_dma_host_set,
+        .dma_setup              = vpac270_dma_setup,
+        .dma_exec_cmd           = vpac270_dma_exec_cmd,
+        .dma_start              = vpac270_dma_start,
+        .dma_end                = vpac270_dma_end,
+        .dma_test_irq           = vpac270_dma_test_irq,
+        .dma_timeout            = vpac270_dma_timeout,
+        .dma_lost_irq           = vpac270_dma_lost_irq,
+};
+
+static const struct ide_port_ops vpac270_port_ops = {
+        .set_dma_mode           = vpac270_set_dma_mode,
+};
+
+static const struct ide_port_info vpac270_port_info __initdata = {
+        .init_dma               = vpac270_dma_off_init,
+        .port_ops               = &vpac270_port_ops,
+        .dma_ops                = &vpac270_dma_ops,
+        .host_flags             = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
+        .mwdma_mask             = ATA_MWDMA2,
+        .swdma_mask             = ATA_SWDMA2,
+};
+
+#define IDE_DATA_OFFSET		0
+#define IDE_STATUS_OFFSET	7
+#define IDE_CONTROL_OFFSET      8
+
+static void vpac270_setup_ports(hw_regs_t *hw, void __iomem *base)
+{
+        int i;
+        unsigned long port = (unsigned long) base;
+
+	for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
+		hw->io_ports_array[i] = (port + 0x120 + 2*i);
+
+	hw->io_ports.ctl_addr = (port + 0x15c);
+}
+
+static int __init vpac270_ide_init(void)
+{
+        void __iomem *base;
+        struct ide_host *host;
+	hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
+
+	printk("Voipac PXA270 IDE driver, (c) 2006 Voipac Technologies\n");
+
+	base = ioremap( IDE_BASE_PHYS, 0x200);;
+
+	if (!base)
+		return -ENOMEM;
+
+        memset(&hw, 0, sizeof(hw));
+        vpac270_setup_ports(&hw, base);
+        hw.irq = VPAC270_IDE_IRQ;
+        hw.chipset = ide_generic;
+
+        return ide_host_add( &vpac270_port_info, hws, &host);
+}
+
+module_init(vpac270_ide_init);
+
+MODULE_AUTHOR("Voipac Technologies <support@voipac.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Voipac PXA270 IDE driver");
+
diff -urN linux-2.6.27/drivers/ide/Kconfig linux-2.6.27-vpac1/drivers/ide/Kconfig
--- linux-2.6.27/drivers/ide/Kconfig	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/ide/Kconfig	2008-11-26 11:30:39.000000000 +0100
@@ -835,6 +835,11 @@
 	help
 	  Enables the H8300 IDE driver.
 
+config BLK_DEV_IDE_VPAC270
+	tristate "Voipac PXA270 IDE support"
+	depends on ARM && (ARCH_PXA || MACH_VPAC270)
+	select BLK_DEV_IDEDMA
+
 config BLK_DEV_GAYLE
 	tristate "Amiga Gayle IDE interface support"
 	depends on AMIGA
diff -urN linux-2.6.27/drivers/leds/Kconfig linux-2.6.27-vpac1/drivers/leds/Kconfig
--- linux-2.6.27/drivers/leds/Kconfig	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/leds/Kconfig	2008-11-26 11:32:32.000000000 +0100
@@ -17,6 +17,13 @@
 
 comment "LED drivers"
 
+config LEDS_VPAC270
+	tristate "LED Support for the Voipac PXA270 baseboard"
+	depends on LEDS_CLASS && MACH_VPAC270
+	help
+	  This option enables support for the LED on Voipac
+	  Technologies PXA270 developement baseboard.
+
 config LEDS_ATMEL_PWM
 	tristate "LED Support using Atmel PWM outputs"
 	depends on LEDS_CLASS && ATMEL_PWM
diff -urN linux-2.6.27/drivers/leds/leds-vpac270.c linux-2.6.27-vpac1/drivers/leds/leds-vpac270.c
--- linux-2.6.27/drivers/leds/leds-vpac270.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.27-vpac1/drivers/leds/leds-vpac270.c	2008-11-26 15:22:30.000000000 +0100
@@ -0,0 +1,91 @@
+/*
+ * LED Triggers Core
+ *
+ * Copyright (c) 2006 Voipac Technologies <support@voipac.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <mach/vpac270.h>
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/mfp-pxa27x.h>
+//#include <asm/hardware/scoop.h>
+
+#define VPAC270_GPIO_LED_ORANGE	GPIO15_nCS_1
+
+static void vpac270led_set(struct led_classdev *led_cdev, enum led_brightness value)
+{
+	if (value)
+		GPSR0 = GPIO_bit(VPAC270_GPIO_LED_ORANGE);
+	else
+		GPCR0 = GPIO_bit(VPAC270_GPIO_LED_ORANGE);
+}
+
+static struct led_classdev vpac270_orange_led = {
+	.name			= "vpac270:orange",
+	.default_trigger	= "heartbeat",
+	.brightness_set		= vpac270led_set,
+};
+
+#ifdef CONFIG_PM
+static int vpac270led_suspend(struct platform_device *dev, pm_message_t state)
+{
+	led_classdev_suspend(&vpac270_orange_led);
+	return 0;
+}
+
+static int vpac270led_resume(struct platform_device *dev)
+{
+	led_classdev_resume(&vpac270_orange_led);
+	return 0;
+}
+#endif
+
+static int vpac270led_probe(struct platform_device *pdev)
+{
+	return led_classdev_register(&pdev->dev, &vpac270_orange_led);
+}
+
+static int vpac270led_remove(struct platform_device *pdev)
+{
+	led_classdev_unregister(&vpac270_orange_led);
+	return 0;
+}
+
+static struct platform_driver vpac270led_driver = {
+	.probe		= vpac270led_probe,
+	.remove		= vpac270led_remove,
+#ifdef CONFIG_PM
+	.suspend	= vpac270led_suspend,
+	.resume		= vpac270led_resume,
+#endif
+	.driver		= {
+		.name		= "vpac270-led",
+	},
+};
+
+static int __init vpac270led_init(void)
+{
+	return platform_driver_register(&vpac270led_driver);
+}
+
+static void __exit vpac270led_exit(void)
+{
+ 	platform_driver_unregister(&vpac270led_driver);
+}
+
+module_init(vpac270led_init);
+module_exit(vpac270led_exit);
+
+MODULE_AUTHOR("Voipac Technologies <support@voipac.com>");
+MODULE_DESCRIPTION("Voipac PXA270 LED driver");
+MODULE_LICENSE("GPL");
diff -urN linux-2.6.27/drivers/leds/Makefile linux-2.6.27-vpac1/drivers/leds/Makefile
--- linux-2.6.27/drivers/leds/Makefile	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/leds/Makefile	2008-11-26 11:34:10.000000000 +0100
@@ -5,6 +5,7 @@
 obj-$(CONFIG_LEDS_TRIGGERS)		+= led-triggers.o
 
 # LED Platform Drivers
+obj-$(CONFIG_LEDS_VPAC270)		+= leds-vpac270.o
 obj-$(CONFIG_LEDS_ATMEL_PWM)		+= leds-atmel-pwm.o
 obj-$(CONFIG_LEDS_CORGI)		+= leds-corgi.o
 obj-$(CONFIG_LEDS_LOCOMO)		+= leds-locomo.o
diff -urN linux-2.6.27/drivers/mtd/onenand/Kconfig linux-2.6.27-vpac1/drivers/mtd/onenand/Kconfig
--- linux-2.6.27/drivers/mtd/onenand/Kconfig	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/mtd/onenand/Kconfig	2008-12-08 16:59:05.000000000 +0100
@@ -27,6 +27,12 @@
 	help
 	  Support for OneNAND flash via platform device driver.
 
+config MTD_ONENAND_PXA27x
+	tristate "PXA27x OneNAND Flash device driver"
+	depends on ARM
+	help
+	  Support for PXA27x OneNAND flash via platform device driver.
+
 config MTD_ONENAND_OTP
 	bool "OneNAND OTP Support"
 	help
diff -urN linux-2.6.27/drivers/mtd/onenand/Makefile linux-2.6.27-vpac1/drivers/mtd/onenand/Makefile
--- linux-2.6.27/drivers/mtd/onenand/Makefile	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/mtd/onenand/Makefile	2008-12-08 17:00:38.000000000 +0100
@@ -8,6 +8,9 @@
 # Board specific.
 obj-$(CONFIG_MTD_ONENAND_GENERIC)	+= generic.o
 
+# PXA27x
+obj-$(CONFIG_MTD_ONENAND_PXA27x)	+= pxa27x_onenand.o
+
 # Simulator
 obj-$(CONFIG_MTD_ONENAND_SIM)		+= onenand_sim.o
 
diff -urN linux-2.6.27/drivers/mtd/onenand/pxa27x_onenand.c linux-2.6.27-vpac1/drivers/mtd/onenand/pxa27x_onenand.c
--- linux-2.6.27/drivers/mtd/onenand/pxa27x_onenand.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.27-vpac1/drivers/mtd/onenand/pxa27x_onenand.c	2008-12-08 17:24:20.000000000 +0100
@@ -0,0 +1,523 @@
+/*
+ *  File: drivers/mtd/onenand/pxa27x-onenand.c
+ *
+ *  Purpose: OneNAND support for the PXA-270.
+ *
+ *  Author:	Pete MacKay
+ *              Axian Consulting
+ *              Beaverton, OR, USA 97005
+ *  Created:	April 9, 2007
+ *  Copyright:	Vernier Software & Technology
+ *              Beaverton, OR, USA 97005
+ *  Web:        www.vernier.com
+ *
+ *  Based on omap2 by Jarkko Lavinen, Juha Yrjola, (Nokia) and Timo Teras
+ *  Based on onenand_base.c by Kyungmin Park (Samsung)
+ *  Based on generic.c by Kyungmin Park (Samsung)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; see the file COPYING. If not, write to the Free Software
+ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ */
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/mach/flash.h>
+
+#include <mach/pxa-regs.h>
+#include <mach/pm.h>
+
+#include <linux/dma-mapping.h>
+#include <asm/dma-mapping.h>
+#include <mach/dma.h>
+
+
+static int no_dma = 0;			// set to disable DMA and use PIO
+module_param (no_dma, int, S_IRUGO);
+
+static int dma_prio = DMA_PRIO_MEDIUM;	// DMA priority: 0 = high, 1 = medium, 2= low
+module_param (dma_prio, int, S_IRUGO);
+
+static int chip_select = -1;		// optional chip select base address mapping: 0-5
+module_param (chip_select, int, S_IRUGO);
+
+static int gpio = -1;			// optional gpio wiring for OneNAND "INT" line
+module_param (gpio, int, S_IRUGO);
+
+struct pxa27x_onenand {
+	struct platform_device *pdev;
+	unsigned long phys_base;
+	int mem_size;
+	int gpio_irq;
+	struct mtd_info mtd;
+	struct mtd_partition *parts;
+	struct onenand_chip onenand;
+	struct completion irq_done;
+	struct completion dma_done;
+	int dma_channel;
+};
+
+
+static void pxa27x_onenand_dma_cb(int lch, void *data)
+{
+	struct pxa27x_onenand *info = data;
+
+	complete(&info->dma_done);
+}
+
+static void dmaxfr(struct pxa27x_onenand *info, dma_addr_t to, dma_addr_t from, size_t len)
+{
+	unsigned int width;
+
+	if (((unsigned long)to & 1) || ((unsigned long)from & 1) || (len & 1)) {
+		width = DCMD_WIDTH1;
+	} else {
+		width = DCMD_WIDTH2;
+	}
+
+	DCSR(info->dma_channel) = 0;		// cancel any running transfers
+	DCSR(info->dma_channel) = DCSR_NODESC;	// not using descriptors
+	DALGN |= (1 << info->dma_channel);	// don't mask 2 LSBs of addresses
+	DSADR(info->dma_channel) = from;	// set source address
+	DTADR(info->dma_channel) = to;		// set destination address
+	DCMD(info->dma_channel) = DCMD_INCTRGADDR | DCMD_INCSRCADDR | DCMD_BURST32 | width | len;
+	DCSR(info->dma_channel) = DCSR_RUN | DCSR_NODESC | DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
+}
+
+
+// this replaces memcpy to ensure 32-bit optimaztion doesn't cause bus errors:
+//
+static void memxfr(void *to, const void *from, size_t len)
+{
+	if (((unsigned long)to & 1) || ((unsigned long)from & 1) || (len & 1)) {
+		u8 *s = (u8 *)from;
+		u8 *d = (u8 *)to;
+
+		while (len--) *(d++) = *(s++);
+	} else {
+		u16 *s = (u16 *)from;
+		u16 *d = (u16 *)to;
+
+		len /= 2;
+		while (len--) *(d++) = *(s++);
+	}
+}
+
+
+static irqreturn_t pxa27x_onenand_interrupt(int irq, void *dev_id)
+{
+	struct pxa27x_onenand *info = dev_id;
+
+	complete(&info->irq_done);
+
+	return IRQ_HANDLED;
+}
+
+static inline unsigned short pxa27x_onenand_readw(void __iomem *addr)
+{
+	return readw(addr);
+}
+
+static inline void pxa27x_onenand_writew(unsigned short value, void __iomem *addr)
+{
+	writew(value, addr);
+}
+
+static int pxa27x_onenand_wait(struct mtd_info *mtd, int state)
+{
+	struct pxa27x_onenand *info = container_of(mtd, struct pxa27x_onenand, mtd);
+	unsigned int interrupt = 0;
+	unsigned int ctrl;
+	unsigned long timeout;
+	u32 syscfg;
+
+	if (state == FL_RESETING) {
+		udelay(1);
+		return 0;
+	}
+
+	if (state != FL_READING) {
+		int result;
+
+		/* Turn interrupts on */
+		syscfg = pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
+		syscfg |= ONENAND_SYS_CFG1_IOBE;
+		pxa27x_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
+
+		INIT_COMPLETION(info->irq_done);
+
+		result = 0;
+//		result = GPLR(info->gpio_irq) & GPIO_bit(info->gpio_irq);
+		if (result == 0) {
+			int retry_cnt = 0;
+
+retry:
+			result = wait_for_completion_timeout( &info->irq_done, msecs_to_jiffies(20));
+			if (result == 0) {
+				/* Timeout after 20ms */
+				ctrl = pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
+				if (ctrl & ONENAND_CTRL_ONGO) {
+					/* The operation seems to be still going - so give it some more time */
+					retry_cnt += 1;
+					if (retry_cnt < 3)
+					goto retry;
+					interrupt = pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
+					printk(KERN_ERR "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
+					return -EIO;
+				}
+				interrupt = pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
+				if ((interrupt & ONENAND_INT_MASTER) == 0)
+					printk(KERN_WARNING "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
+			}
+		}
+	} else {
+		/* Turn interrupts off */
+		syscfg = pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
+		syscfg &= ~ONENAND_SYS_CFG1_IOBE;
+		pxa27x_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
+
+		timeout = jiffies + msecs_to_jiffies(20);
+		while (time_before(jiffies, timeout)) {
+			if (pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT) &
+			ONENAND_INT_MASTER)
+				break;
+		}
+	}
+
+	/* To get correct interrupt status in timeout case */
+	interrupt = pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
+	ctrl = pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
+
+	if (ctrl & ONENAND_CTRL_ERROR) {
+		printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl);
+		if (ctrl & ONENAND_CTRL_LOCK)
+			printk(KERN_ERR "onenand_erase: Device is write protected!!!\n");
+		return ctrl;
+	}
+
+	if (ctrl & 0xFE9F)
+		printk(KERN_WARNING "onenand_wait: unexpected controller status = 0x%04x state = %d interrupt = 0x%04x\n", ctrl, state, interrupt);
+
+	if (interrupt & ONENAND_INT_READ) {
+		int ecc = pxa27x_onenand_readw(info->onenand.base + ONENAND_REG_ECC_STATUS);
+
+		if (ecc) {
+			printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc);
+			if (ecc & ONENAND_ECC_2BIT_ALL) {
+			mtd->ecc_stats.failed++;
+			return ecc;
+		} else if (ecc & ONENAND_ECC_1BIT_ALL)
+			mtd->ecc_stats.corrected++;
+		}
+	} else if (state == FL_READING) {
+		printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static inline int pxa27x_onenand_bufferram_offset(struct mtd_info *mtd, int area)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this)) {
+		if (area == ONENAND_DATARAM) return mtd->writesize;
+		if (area == ONENAND_SPARERAM) return mtd->oobsize;
+	}
+
+	return 0;
+}
+
+static int pxa27x_onenand_read_bufferram(struct mtd_info *mtd, int area,
+	unsigned char *buffer, int offset, size_t count)
+{
+	struct pxa27x_onenand *info = container_of(mtd, struct pxa27x_onenand, mtd);
+	struct onenand_chip *this = mtd->priv;
+	struct device *dev = &info->pdev->dev;
+	dma_addr_t dma_src, dma_dst;
+	int bram_offset;
+
+	bram_offset = pxa27x_onenand_bufferram_offset(mtd, area) + area + offset;
+	if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
+	(bram_offset & 3) || (((unsigned int) buffer) & 3) ||
+	(count < 1024) || (count & 3)) {
+		memxfr(buffer, (void *)(this->base + bram_offset), count);
+		return 0;
+	}
+
+	dma_src = info->phys_base + bram_offset;
+	dma_dst = dma_map_single(dev, buffer, count, DMA_FROM_DEVICE);
+	if (dma_mapping_error(dev, dma_dst)) {
+		dev_err(dev,
+		"Couldn't DMA map a %d byte buffer\n",
+		count);
+		return -1;
+	}
+
+	INIT_COMPLETION(info->dma_done);
+	dmaxfr(info, dma_dst, dma_src, count);
+	wait_for_completion(&info->dma_done);
+
+	dma_unmap_single(dev, dma_dst, count, DMA_FROM_DEVICE);
+
+	return 0;
+}
+
+static int pxa27x_onenand_write_bufferram(struct mtd_info *mtd, int area,
+	const unsigned char *buffer, int offset, size_t count)
+{
+	struct pxa27x_onenand *info = container_of(mtd, struct pxa27x_onenand, mtd);
+	struct onenand_chip *this = mtd->priv;
+	struct device *dev = &info->pdev->dev;
+	dma_addr_t dma_src, dma_dst;
+	int bram_offset;
+
+	bram_offset = pxa27x_onenand_bufferram_offset(mtd, area) + area + offset;
+	if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
+	(bram_offset & 3) || (((unsigned int) buffer) & 3) ||
+	(count < 1024) || (count & 3)) {
+		memxfr((void *)(this->base + bram_offset), (void *)buffer, count);
+		return 0;
+	}
+
+	dma_src = dma_map_single(dev, (void *) buffer, count, DMA_TO_DEVICE);
+	dma_dst = info->phys_base + bram_offset;
+	if (dma_mapping_error(dev, dma_dst)) {
+		dev_err(dev, "Couldn't DMA map a %d byte buffer\n", count);
+		return -1;
+	}
+
+	INIT_COMPLETION(info->dma_done);
+	dmaxfr(info, dma_dst, dma_src, count);
+	wait_for_completion(&info->dma_done);
+
+	dma_unmap_single(dev, dma_dst, count, DMA_TO_DEVICE);
+
+	return 0;
+}
+
+static int __devinit pxa27x_onenand_probe(struct platform_device *pdev)
+{
+#ifdef CONFIG_MTD_CMDLINE_PARTS
+	const char *probes[] = { "cmdlinepart", NULL };
+#else
+	const char *probes[] = { NULL };
+#endif
+	struct flash_platform_data *pdata = pdev->dev.platform_data;
+	struct resource *res = pdev->resource;
+	struct pxa27x_onenand *info;
+	int r;
+
+
+	// virgin OneNAND data structure:
+	//
+	info = kzalloc(sizeof(struct pxa27x_onenand), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+	info->pdev = pdev;
+
+
+	// find memory location and map it:
+	//
+	info->mem_size = SZ_128K;
+	switch (chip_select) {
+	case 0:
+		info->phys_base = PXA_CS0_PHYS;
+		break;
+	case 1:
+		info->phys_base = PXA_CS1_PHYS;
+		break;
+	case 2:
+		info->phys_base = PXA_CS2_PHYS;
+		break;
+	case 3:
+		info->phys_base = PXA_CS3_PHYS;
+		break;
+	case 4:
+		info->phys_base = PXA_CS4_PHYS;
+		break;
+	case 5:
+		info->phys_base = PXA_CS5_PHYS;
+		break;
+	default:
+		info->phys_base = res->start;
+		info->mem_size = res->end - res->start + 1;
+		break;
+	}
+
+	if (request_mem_region(info->phys_base, info->mem_size, pdev->dev.driver->name) == NULL) {
+		dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n", info->phys_base, info->mem_size);
+		r = -EBUSY;
+		goto err_kfree;
+	}
+
+	info->onenand.base = ioremap(info->phys_base, info->mem_size);
+	if (info->onenand.base == NULL) {
+		r = -ENOMEM;
+		goto err_release_mem_region;
+	}
+
+	dev_info(&pdev->dev, "initializing at phys base 0x%08lx, virtual base %p\n",
+		info->phys_base, info->onenand.base);
+
+
+	// configure interrupt handler:
+	//
+	init_completion(&info->irq_done);
+	if (gpio == -1) {
+		info->gpio_irq = platform_get_irq(pdev, 0);
+	} else {
+		pxa_gpio_mode(gpio);	// GPIO_IN
+		info->gpio_irq = IRQ_GPIO(gpio);
+	}
+	if ((r = request_irq( info->gpio_irq,
+		pxa27x_onenand_interrupt, IRQF_TRIGGER_RISING,
+		pdev->dev.driver->name, info)) < 0)
+		goto err_iounmap;
+
+
+	// configure DMA channel and setup transfers:
+	//
+	init_completion(&info->dma_done);
+	if (no_dma) {
+		info->dma_channel = -1;
+	} else {
+		if ((unsigned)dma_prio > DMA_PRIO_LOW) dma_prio = DMA_PRIO_LOW;
+		info->dma_channel = pxa_request_dma ( (char *)pdev->dev.driver->name, dma_prio,
+			 pxa27x_onenand_dma_cb, (void *)info);
+	}
+
+	if (info->dma_channel == -1) {
+		dev_info(&pdev->dev,"failed to allocate DMA for OneNAND, using PIO instead\n");
+	} else {
+		dev_info(&pdev->dev,"using DMA channel %d for OneNAND\n", info->dma_channel);
+	}
+
+
+	// fill in chip functions:
+	//
+	info->onenand.wait = pxa27x_onenand_wait;
+	info->onenand.read_bufferram = pxa27x_onenand_read_bufferram;
+	info->onenand.write_bufferram = pxa27x_onenand_write_bufferram;
+
+
+	// fill in MTD details:
+	//
+	info->mtd.name = pdev->dev.bus_id;
+	info->mtd.priv = &info->onenand;
+	info->mtd.owner = THIS_MODULE;
+
+	if ((r = onenand_scan(&info->mtd, 1)) < 0)
+	goto err_release_dma;
+
+#ifdef CONFIG_MTD_PARTITIONS
+	r = parse_mtd_partitions(&info->mtd, probes, &info->parts, 0);
+	if (r) {
+		DEBUG( MTD_DEBUG_LEVEL1,
+			"Using command line partitions on %s\n", pdev->dev.driver->name);
+		r = add_mtd_partitions(&info->mtd, info->parts, r);
+	} else if (pdata->parts) {
+		info->parts = pdata->parts;
+		DEBUG( MTD_DEBUG_LEVEL1,
+			"Using static partitions on %s\n", pdev->dev.driver->name);
+		r = add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
+	} else {
+		DEBUG( MTD_DEBUG_LEVEL1,
+			"No partitions found on %s\n", pdev->dev.driver->name);
+		r = add_mtd_partitions(&info->mtd, info->parts, r);
+	}
+#else
+	r = add_mtd_device(&info->mtd);
+#endif
+	if (r < 0)
+		goto err_release_onenand;
+
+	platform_set_drvdata(pdev, info);
+	return r;
+
+err_release_onenand:
+	onenand_release(&info->mtd);
+err_release_dma:
+	if (info->dma_channel != -1)
+		pxa_free_dma(info->dma_channel);
+	free_irq(info->gpio_irq, info);
+err_iounmap:
+	iounmap(info->onenand.base);
+err_release_mem_region:
+	release_mem_region(info->phys_base, info->mem_size);
+err_kfree:
+	kfree(info);
+
+	return r;
+}
+
+static int __devexit pxa27x_onenand_remove(struct platform_device *pdev)
+{
+	struct pxa27x_onenand *info = dev_get_drvdata(&pdev->dev);
+
+	BUG_ON(info == NULL);
+
+#ifdef CONFIG_MTD_PARTITIONS
+	if (info->parts)
+		del_mtd_partitions(&info->mtd);
+	else
+		del_mtd_device(&info->mtd);
+#else
+	del_mtd_device(&info->mtd);
+#endif
+	onenand_release(&info->mtd);
+
+	if (info->dma_channel != -1)
+		pxa_free_dma(info->dma_channel);
+	platform_set_drvdata(pdev, NULL);
+	free_irq(info->gpio_irq, info);
+	iounmap(info->onenand.base);
+	release_mem_region(info->phys_base, info->mem_size);
+	kfree(info);
+
+	return 0;
+}
+
+static struct platform_driver pxa27x_onenand_driver = {
+	.probe = pxa27x_onenand_probe,
+	.remove = pxa27x_onenand_remove,
+	.driver = {
+		.name = "onenand",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init pxa27x_onenand_init(void)
+{
+	return platform_driver_register(&pxa27x_onenand_driver);
+}
+
+static void __exit pxa27x_onenand_exit(void)
+{
+	platform_driver_unregister(&pxa27x_onenand_driver);
+}
+
+module_init(pxa27x_onenand_init);
+module_exit(pxa27x_onenand_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Pete MacKay");
+MODULE_DESCRIPTION("Glue layer for OneNAND flash on PXA-27x machines");
diff -urN linux-2.6.27/drivers/net/wireless/hostap/hostap_cs.c linux-2.6.27-vpac1/drivers/net/wireless/hostap/hostap_cs.c
--- linux-2.6.27/drivers/net/wireless/hostap/hostap_cs.c	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/net/wireless/hostap/hostap_cs.c	2008-11-26 11:43:01.000000000 +0100
@@ -31,7 +31,7 @@
 MODULE_LICENSE("GPL");
 
 
-static int ignore_cis_vcc;
+static int ignore_cis_vcc = 1;
 module_param(ignore_cis_vcc, int, 0444);
 MODULE_PARM_DESC(ignore_cis_vcc, "Ignore broken CIS VCC entry");
 
@@ -826,6 +826,7 @@
 	PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777),
 	PCMCIA_DEVICE_MANF_CARD(0x0126, 0x8000),
 	PCMCIA_DEVICE_MANF_CARD(0x0138, 0x0002),
+	PCMCIA_DEVICE_MANF_CARD(0x0156, 0x0002),
 	PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x3301),
 	PCMCIA_DEVICE_MANF_CARD(0x0250, 0x0002),
 	PCMCIA_DEVICE_MANF_CARD(0x026f, 0x030b),
@@ -839,7 +840,9 @@
 /*	PCMCIA_DEVICE_MANF_CARD(0xc00f, 0x0000),    conflict with pcnet_cs */
 	PCMCIA_DEVICE_MANF_CARD(0xc250, 0x0002),
 	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0002),
+	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0004),
 	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0005),
+	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0007),
 	PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0010),
 	PCMCIA_DEVICE_MANF_CARD(0x0126, 0x0002),
 	PCMCIA_DEVICE_MANF_CARD_PROD_ID1(0xd601, 0x0005, "ADLINK 345 CF",
diff -urN linux-2.6.27/drivers/pcmcia/Kconfig linux-2.6.27-vpac1/drivers/pcmcia/Kconfig
--- linux-2.6.27/drivers/pcmcia/Kconfig	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/pcmcia/Kconfig	2008-11-26 16:33:35.000000000 +0100
@@ -220,7 +220,7 @@
 	tristate "PXA2xx support"
 	depends on ARM && ARCH_PXA && PCMCIA
 	depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \
-		    || MACH_ARMCORE || ARCH_PXA_PALM)
+		    || MACH_ARMCORE || ARCH_PXA_PALM || MACH_VPAC270)
 	help
 	  Say Y here to include support for the PXA2xx PCMCIA controller
 
diff -urN linux-2.6.27/drivers/pcmcia/Makefile linux-2.6.27-vpac1/drivers/pcmcia/Makefile
--- linux-2.6.27/drivers/pcmcia/Makefile	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/pcmcia/Makefile	2008-11-26 11:40:23.000000000 +0100
@@ -72,5 +72,6 @@
 pxa2xx_cs-$(CONFIG_MACH_MAINSTONE)		+= pxa2xx_mainstone.o
 pxa2xx_cs-$(CONFIG_PXA_SHARPSL)			+= pxa2xx_sharpsl.o
 pxa2xx_cs-$(CONFIG_MACH_ARMCORE)		+= pxa2xx_cm_x270.o
+pxa2xx_cs-$(CONFIG_MACH_VPAC270)		+= pxa2xx_vpac270.o
 pxa2xx_cs-$(CONFIG_MACH_PALMTX)		+= pxa2xx_palmtx.o
 
diff -urN linux-2.6.27/drivers/pcmcia/pxa2xx_vpac270.c linux-2.6.27-vpac1/drivers/pcmcia/pxa2xx_vpac270.c
--- linux-2.6.27/drivers/pcmcia/pxa2xx_vpac270.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.27-vpac1/drivers/pcmcia/pxa2xx_vpac270.c	2009-01-03 02:45:09.000000000 +0100
@@ -0,0 +1,240 @@
+/*
+ * linux26/drivers/pcmcia/pxa2xx_vpac270.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) 2002 Accelent Systems, Inc. All Rights Reserved
+ * Copyright (c) 2006 Voipac Technologies <support@voipac.com>
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+
+#include <pcmcia/ss.h>
+
+#include <asm/delay.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <mach/vpac270.h>
+#include <mach/pxa2xx-gpio.h>
+
+#include "soc_common.h"
+
+//#define DEBUG_COL_PCMCIA
+
+#ifdef DEBUG_COL_PCMCIA
+#define MARK printk(KERN_INFO "%s: %d\n", __FUNCTION__, __LINE__);
+#else
+//#define MARK (0)
+#endif
+#ifdef PCMCIA_DEBUG
+int pc_debug = PCMCIA_DEBUG;
+#endif
+
+static struct pcmcia_irqs irqs[] = {
+    { 0, VPAC270_PCMCIA0_CD_IRQ, "CF CD"},
+    { 1, VPAC270_PCMCIA1_CD_IRQ, "PCMCIA CD"},
+};
+
+
+static int vpac270_pcmcia_init_dev(struct soc_pcmcia_socket *skt)
+{
+    printk("Voipac PXA270 PCMCIA\n");
+    /* set power GPIO; switch off */
+    GPCR(GPIO_PCMCIA_POW_EN) |= GPIO_bit(GPIO_PCMCIA_POW_EN);
+    GPDR(GPIO_PCMCIA_POW_EN) |= GPIO_bit(GPIO_PCMCIA_POW_EN);
+
+    /* set PCMCIA AFs */
+    GPSR(GPIO_PCMCIA_NPOE) |= GPIO_bit(GPIO_PCMCIA_NPOE);
+    pxa_gpio_mode(GPIO_PCMCIA_NPOE | GPIO_PCMCIA_NPOE_AF);
+
+    GPSR(GPIO_PCMCIA_NPIOR) |= GPIO_bit(GPIO_PCMCIA_NPIOR);
+    pxa_gpio_mode(GPIO_PCMCIA_NPIOR | GPIO_PCMCIA_NPIOR_AF);
+
+    GPSR(GPIO_PCMCIA_NPIOW) |= GPIO_bit(GPIO_PCMCIA_NPIOW);
+    pxa_gpio_mode(GPIO_PCMCIA_NPIOW | GPIO_PCMCIA_NPIOW_AF);
+
+    GPSR(GPIO_PCMCIA_NPCE1) |= GPIO_bit(GPIO_PCMCIA_NPCE1);
+    pxa_gpio_mode(GPIO_PCMCIA_NPCE1 | GPIO_PCMCIA_NPCE1_AF);
+
+    GPCR(GPIO_PCMCIA_NPCE2) |= GPIO_bit(GPIO_PCMCIA_NPCE2);
+    pxa_gpio_mode(GPIO_PCMCIA_NPCE2 | GPIO_PCMCIA_NPCE2_AF);
+
+    GPSR(GPIO_PCMCIA_NPREG) |= GPIO_bit(GPIO_PCMCIA_NPREG);
+    pxa_gpio_mode(GPIO_PCMCIA_NPREG | GPIO_PCMCIA_NPREG_AF);
+
+    pxa_gpio_mode(GPIO_PCMCIA_NPWAIT | GPIO_PCMCIA_NPWAIT_AF);
+
+    pxa_gpio_mode(GPIO_PCMCIA_NPIOIS16 | GPIO_PCMCIA_NPIOIS16_AF);
+
+    GPSR(GPIO_PCMCIA_PSKTSEL) |= GPIO_bit(GPIO_PCMCIA_PSKTSEL);
+    pxa_gpio_mode(GPIO_PCMCIA_PSKTSEL | GPIO_PCMCIA_PSKTSEL_AF);
+
+    /* set other PCMCIA GPIOs */
+    GPCR(GPIO_PCMCIA0_RESET) |= GPIO_bit(GPIO_PCMCIA0_RESET);
+    GPDR(GPIO_PCMCIA0_RESET) |= GPIO_bit(GPIO_PCMCIA0_RESET);
+    GPCR(GPIO_PCMCIA1_RESET) |= GPIO_bit(GPIO_PCMCIA1_RESET);
+    GPDR(GPIO_PCMCIA1_RESET) |= GPIO_bit(GPIO_PCMCIA1_RESET);
+
+//    GPDR(GPIO_PCMCIA0_BVD1) &= ~GPIO_bit(GPIO_PCMCIA0_BVD1);
+//    GPDR(GPIO_PCMCIA0_BVD2) &= ~GPIO_bit(GPIO_PCMCIA0_BVD2);
+
+    /* switch power on */
+    PCC_PWR_ON();
+
+    /* set interrupts */
+	GPDR(GPIO_PCMCIA0_CD_IRQ) &= ~GPIO_bit(GPIO_PCMCIA0_CD_IRQ);
+	GPDR(GPIO_PCMCIA0_RDY_IRQ) &= ~GPIO_bit(GPIO_PCMCIA0_RDY_IRQ);
+	GPDR(GPIO_PCMCIA1_CD_IRQ) &= ~GPIO_bit(GPIO_PCMCIA1_CD_IRQ);
+	GPDR(GPIO_PCMCIA1_RDY_IRQ) &= ~GPIO_bit(GPIO_PCMCIA1_RDY_IRQ);
+
+        if (skt->irq == NO_IRQ)
+                skt->irq = skt->nr ? VPAC270_PCMCIA1_RDY_IRQ : VPAC270_PCMCIA0_RDY_IRQ;
+
+        return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
+}
+
+static void vpac270_pcmcia_shutdown(struct soc_pcmcia_socket *skt)
+{
+	soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
+
+    /* switch power off */
+    PCC_PWR_OFF();
+}
+
+static void vpac270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
+                                        struct pcmcia_state *state)
+{
+	//memset(state, 0, sizeof(*state));
+
+	switch( skt->nr)
+	{
+	case 0:
+		state->detect = (PCC0_DETECT) ? 0 : 1;
+		state->ready =  (PCC0_READY) ? 1 : 0;
+		break;
+
+	case 1:
+		state->detect = (PCC1_DETECT) ? 0 : 1;
+		state->ready =  (PCC1_READY) ? 1 : 0;
+		break;
+
+	default:
+		return;
+	}
+/*
+    printk(KERN_INFO "CF status: detect: %u, ready: %u\n",
+           GPLR(84) & GPIO_bit(84),
+           GPLR(1) & GPIO_bit(1));
+*/
+
+	state->bvd1   = 1;	//PCC_BVD1() ? 1 : 0;
+	state->bvd2   = 1;	//PCC_BVD2() ? 1 : 0;
+	state->wrprot = 0; /* r/w all the time */
+	state->vs_3v  = PCC_VS3V() ? 1 : 0;
+	state->vs_Xv  = PCC_VS5V() ? 1 : 0;
+}
+
+static int vpac270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
+                                           socket_state_t const *state)
+{
+    unsigned long flags;
+
+    local_irq_save(flags);
+	/* configure Vcc and Vpp */
+    if (state->Vcc == 0 && state->Vpp == 0)
+    {
+        PCC_PWR_OFF();
+    }
+    else if (state->Vcc == 33 && state->Vpp < 50)
+    {
+        PCC_PWR_ON();
+    }
+    else
+    {
+        printk(KERN_ERR "%s(): unsupported Vcc %u Vpp %u combination\n",
+               __FUNCTION__, state->Vcc, state->Vpp);
+        return -1;
+    }
+
+    /* reset PCMCIA if requested */
+    if (state->flags & SS_RESET)
+    {
+	if( skt->nr == 0)
+	    GPSR(GPIO_PCMCIA0_RESET) |= GPIO_bit(GPIO_PCMCIA0_RESET);
+	else
+	    GPSR(GPIO_PCMCIA1_RESET) |= GPIO_bit(GPIO_PCMCIA1_RESET);
+    } else {
+	if( skt->nr == 0)
+	    GPCR(GPIO_PCMCIA0_RESET) |= GPIO_bit(GPIO_PCMCIA0_RESET);
+	else
+	    GPCR(GPIO_PCMCIA1_RESET) |= GPIO_bit(GPIO_PCMCIA1_RESET);
+    }
+
+    local_irq_restore(flags);
+    udelay(200);
+
+	return 0;
+}
+
+static void vpac270_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
+{
+}
+
+static void vpac270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
+{
+}
+
+struct pcmcia_low_level vpac270_pcmcia_ops = { 
+    .owner             = THIS_MODULE,
+    .hw_init           = vpac270_pcmcia_init_dev,
+    .hw_shutdown       = vpac270_pcmcia_shutdown,
+    .socket_state      = vpac270_pcmcia_socket_state,
+    .configure_socket  = vpac270_pcmcia_configure_socket,
+    .socket_init       = vpac270_pcmcia_socket_init,
+    .socket_suspend    = vpac270_pcmcia_socket_suspend,
+    .first             = 0,
+    .nr                = 2
+};
+
+static struct platform_device *vpac270_pcmcia_device;
+
+static int __init vpac270_pcmcia_init(void)
+{
+    int ret;
+
+    vpac270_pcmcia_device = kmalloc(sizeof(*vpac270_pcmcia_device), GFP_KERNEL);
+    if (!vpac270_pcmcia_device)
+        return -ENOMEM;
+    memset(vpac270_pcmcia_device, 0, sizeof(*vpac270_pcmcia_device));
+    vpac270_pcmcia_device->name = "pxa2xx-pcmcia";
+    vpac270_pcmcia_device->dev.platform_data = &vpac270_pcmcia_ops;
+
+    ret = platform_device_register(vpac270_pcmcia_device);
+    if (ret)
+        kfree(vpac270_pcmcia_device);
+
+    return ret;
+}
+
+static void __exit vpac270_pcmcia_exit(void)
+{
+    /* Are there still references to vpac270_pcmcia_device?
+     * I don't know, so I'd better not free it.
+     * Actually, I don't really care, as I don't really support
+     * this driver as module anyway...
+     */
+    platform_device_unregister(vpac270_pcmcia_device);
+}
+
+module_init(vpac270_pcmcia_init);
+module_exit(vpac270_pcmcia_exit);
+
+MODULE_DESCRIPTION("Voipac PXA270 CF Support");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Voipac Technologies <support@voipac.com>");
diff -urN linux-2.6.27/drivers/video/Kconfig linux-2.6.27-vpac1/drivers/video/Kconfig
--- linux-2.6.27/drivers/video/Kconfig	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/video/Kconfig	2008-11-26 12:53:18.000000000 +0100
@@ -1797,6 +1797,54 @@
 
 	  If unsure, say N.
 
+choice
+
+	depends on FB_PXA
+	prompt  "PXA framebuffer device"
+	default FB_PXA_ANALOG
+
+config FB_PXA_ANALOG
+	bool "Analog DAC output"
+
+config FB_PXA_TX14D14VM1BBA
+	bool "HITACHI TX14D14VM1BBA (640x480)"
+
+config FB_PXA_FG0700A0DSSWAGT1
+        bool "DATA IMAGE FG0700A0DSSWAGT1 (800x480)"
+
+endchoice
+
+choice
+
+	depends on FB_PXA && FB_PXA_ANALOG
+	prompt "PXA framebuffer resolution"
+	default FB_PXA_SVGA
+
+config FB_PXA_VGA
+	bool "VGA 640x480"
+
+config FB_PXA_SVGA
+	bool "SVGA 800x600"
+
+config FB_PXA_XGA
+	bool "XGA 1024x768"
+
+endchoice
+
+choice
+
+	depends on FB_PXA && FB_PXA_ANALOG
+	prompt "PXA framebuffer bits per pixel"
+	default FB_PXA_BPP16
+
+config FB_PXA_BPP8
+	bool "8 bpp"
+
+config FB_PXA_BPP16
+	bool "16 bpp"
+
+endchoice
+
 config FB_PXA_SMARTPANEL
 	bool "PXA Smartpanel LCD support"
 	default n
diff -urN linux-2.6.27/drivers/video/pxafb.c linux-2.6.27-vpac1/drivers/video/pxafb.c
--- linux-2.6.27/drivers/video/pxafb.c	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/drivers/video/pxafb.c	2009-01-02 15:18:51.000000000 +0100
@@ -57,6 +57,7 @@
 /*
  * Complain if VAR is out of range.
  */
+//#define pr_debug printk
 #define DEBUG_VAR 1
 
 #include "pxafb.h"
@@ -945,7 +946,7 @@
 		setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
 
 	fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
-	fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
+	fbi->reg_lccr4 |= (fbi->lccr4 & (LCCR4_PCD_DIV_MASK | LCCR4_PAL_FOR_MASK));
 	local_irq_restore(flags);
 
 	/*
@@ -1045,6 +1046,7 @@
 	pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
 	pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
 	pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
+	pr_debug("reg_lccr4 0x%08x\n", (unsigned int) fbi->reg_lccr4);
 
 	/* enable LCD controller clock */
 	clk_enable(fbi->clk);
@@ -1053,6 +1055,7 @@
 		return;
 
 	/* Sequence from 11.7.10 */
+	lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
 	lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
 	lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
 	lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
@@ -1677,7 +1680,7 @@
 #define pxafb_setup_options()		(0)
 #endif
 
-#ifdef DEBUG_VAR
+#if DEBUG_VAR
 /* Check for various illegal bit-combinations. Currently only
  * a warning is given. */
 static void __devinit pxafb_check_options(struct device *dev,
diff -urN linux-2.6.27/Makefile linux-2.6.27-vpac1/Makefile
--- linux-2.6.27/Makefile	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/Makefile	2008-12-15 11:03:21.000000000 +0100
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 27
-EXTRAVERSION =
+EXTRAVERSION = -vpac1
 NAME = Rotary Wombat
 
 # *DOCUMENTATION*
@@ -190,8 +190,9 @@
 # Default value for CROSS_COMPILE is not to prefix executables
 # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile
 export KBUILD_BUILDHOST := $(SUBARCH)
-ARCH		?= $(SUBARCH)
-CROSS_COMPILE	?=
+ARCH		?= arm
+CROSS_COMPILE	?= arm-linux-
+#CROSS_COMPILE	?= arm-none-linux-gnueabi-
 
 # Architecture as present in compile.h
 UTS_MACHINE 	:= $(ARCH)
diff -urN linux-2.6.27/sound/arm/pxa2xx-ac97.c linux-2.6.27-vpac1/sound/arm/pxa2xx-ac97.c
--- linux-2.6.27/sound/arm/pxa2xx-ac97.c	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1/sound/arm/pxa2xx-ac97.c	2008-11-26 16:00:23.000000000 +0100
@@ -156,10 +156,12 @@
 #ifdef CONFIG_PXA27x
 		/* warm reset broken on Bulverde,
 		   so manually keep AC97 reset high */
-		pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 
+//		pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH); 
+		pxa_gpio_mode( 95 | GPIO_OUT | GPIO_DFLT_HIGH);
 		udelay(10);
 		GCR |= GCR_WARM_RST;
-		pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+//		pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+		pxa_gpio_mode( 95 | GPIO_ALT_FN_1_OUT);
 		udelay(500);
 #elif defined(CONFIG_PXA3xx)
 		timeout = 100;
@@ -177,6 +179,9 @@
 					 __func__, gsr_bits);
 	}
 
+	pxa2xx_ac97_write(ac97, 0x6a, 0x0050);
+	pxa2xx_ac97_write(ac97, 0x6c, 0x0030);
+
 	GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
 	GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
 }
@@ -364,7 +369,9 @@
 	pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
 #ifdef CONFIG_PXA27x
 	/* Use GPIO 113 as AC97 Reset on Bulverde */
-	pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+//	pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
+	pxa_gpio_mode( 95 | GPIO_ALT_FN_1_OUT);
+	pxa_gpio_mode( 98 | GPIO_ALT_FN_1_OUT);
 	ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
 	if (IS_ERR(ac97conf_clk)) {
 		ret = PTR_ERR(ac97conf_clk);
diff -urN linux-2.6.27-vpac1/arch/arm/configs/vpac270_defconfig linux-2.6.27-vpac1-256/arch/arm/configs/vpac270_defconfig
--- linux-2.6.27-vpac1/arch/arm/configs/vpac270_defconfig	2009-01-07 16:56:38.000000000 +0100
+++ linux-2.6.27-vpac1-256/arch/arm/configs/vpac270_defconfig	2009-01-07 17:10:57.000000000 +0100
@@ -261,7 +261,7 @@
 # Boot options
 #
 CONFIG_ZBOOT_ROM_TEXT=0x20000
-CONFIG_ZBOOT_ROM_BSS=0xa0800000
+CONFIG_ZBOOT_ROM_BSS=0x80800000
 CONFIG_ZBOOT_ROM=y
 CONFIG_CMDLINE="mem=32M root=/dev/nfs ip=dhcp console=ttyS0,38400"
 # CONFIG_KEXEC is not set
diff -urN linux-2.6.27-vpac1/arch/arm/include/asm/memory.h linux-2.6.27-vpac1-256/arch/arm/include/asm/memory.h
--- linux-2.6.27-vpac1/arch/arm/include/asm/memory.h	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1-256/arch/arm/include/asm/memory.h	2009-01-02 14:53:10.000000000 +0100
@@ -34,7 +34,7 @@
  * TASK_SIZE - the maximum size of a user space task.
  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
  */
-#define TASK_SIZE		UL(0xbf000000)
+#define TASK_SIZE		UL(0x9f000000)
 #define TASK_UNMAPPED_BASE	UL(0x40000000)
 #endif
 
@@ -44,10 +44,10 @@
 #define TASK_SIZE_26		UL(0x04000000)
 
 /*
- * Page offset: 3GB
+ * Page offset: 2.5GB
  */
 #ifndef PAGE_OFFSET
-#define PAGE_OFFSET		UL(0xc0000000)
+#define PAGE_OFFSET		UL(0xa0000000)
 #endif
 
 /*
diff -urN linux-2.6.27-vpac1/arch/arm/mach-pxa/include/mach/memory.h linux-2.6.27-vpac1-256/arch/arm/mach-pxa/include/mach/memory.h
--- linux-2.6.27-vpac1/arch/arm/mach-pxa/include/mach/memory.h	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1-256/arch/arm/mach-pxa/include/mach/memory.h	2009-01-02 14:50:55.000000000 +0100
@@ -15,7 +15,7 @@
 /*
  * Physical DRAM offset.
  */
-#define PHYS_OFFSET	UL(0xa0000000)
+#define PHYS_OFFSET	UL(0x80000000)
 
 /*
  * Virtual view <-> DMA view memory address translations
@@ -37,7 +37,7 @@
  *
  * This needs a node mem size of 26 bits.
  */
-#define NODE_MEM_SIZE_BITS	26
+#define NODE_MEM_SIZE_BITS	28
 
 #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
 void cmx270_pci_adjust_zones(int node, unsigned long *size,
diff -urN linux-2.6.27-vpac1/arch/arm/mach-pxa/Makefile.boot linux-2.6.27-vpac1-256/arch/arm/mach-pxa/Makefile.boot
--- linux-2.6.27-vpac1/arch/arm/mach-pxa/Makefile.boot	2008-10-10 00:13:53.000000000 +0200
+++ linux-2.6.27-vpac1-256/arch/arm/mach-pxa/Makefile.boot	2009-01-02 14:48:07.000000000 +0100
@@ -1,2 +1,2 @@
-   zreladdr-y	:= 0xa0008000
+   zreladdr-y	:= 0x80008000
 
